[1] [1] SONG M K, CHEN L, SANKMAN J, et al. On-chip HV bootstrap gate driving for GaN compatible power circuits operating above 10 MHz ［J］. IEEE J Sol Sta Circ, 2022, 57(3): 942-952.

[2] [2] MING X, LIN Z Y, SUN T, et al. Anup to 10 MHz 6.8% minimum duty ratio GaN driver with dual-mos-switches bootstrap and adaptive short-pulse based high-CMTI level shifter achieving 6.05% efficiency improvement ［C］// IEEE CICC. Newport Beach, CA, USA. 2022: 1-2.

[3] [3] MING X, ZHANG X, ZHANG Z W, et al. A high-reliability half-bridge GaN FET gate driver with advanced floating bias control techniques ［C］// IEEE 31st Int Symp Power Semicond Dev & IC. Shanghai, China. 2019: 127-130.

[4] [4] LU Y, ZHU J, SUN W, et al. A 600 V high-side gate drive circuit with ultra-low propagation delay for enhancement mode GaN devices ［C］// IEEE 30th Int Symp Power Semicond Dev & IC. Chicago, IR, USA. 2018: 80-83.

[5] [5] NGUYEN V H, LY N, ALAMEH A H, et al. Aversatile 200-V capacitor-coupled level shifter for fully floating multi-MHz gate drivers ［J］. IEEE Trans Circ Syst II: Expr Brie, 2021, 68(5): 1625-1629.

[6] [6] MOGHE Y, LEHMANN T,PIESSENS T. Nanosecond delay floating high voltage level shifters in a 0.35 μm HV-CMOS technology ［J］. IEEE J Sol Sta Circ, 2011, 46(2): 485-497.

[7] [7] CAO J W, ZHOU Z K, WANG Z, et al. Design techniques of sub-ns level shifters with ultrahigh dV/dt immunity for various wide-bandgap applications ［J］. IEEE Trans Power Elec, 2021, 36(9): 10447-10460.

[8] [8] LIU D W, HOLLIS S J, DYMOND H C P, et al. Design of 370-ps delay floating-voltage level shifters with 30-V/ns power supply slew tolerance ［J］. IEEE Trans Circ Syst II: Expr Brie, 2016, 63(7): 688-692.

[9] [9] LIU Z D, CONG L, LEE H. Design of on-chip gate drivers with power-efficient high-speed level shifting and dynamic timing control for high-voltage synchronous switching power converters ［J］. IEEE J Sol Sta Circ, 2015, 50(6): 1463-1477.

[10] [10] ABDELMOATY A, AL-SHYOUKH M, FAYED A. A high-voltage level shifter with sub-nanosecond propagation delay for switching power converters ［C］// IEEE APEC. Long Beach, CA, USA. 2016: 2437-2440.

[11] [11] LUTZ D, SEIDEL A, WICHT B. A 50 V, 1.45 ns, 4.1 pJ high-speed low-power level shifter for high-voltage DCDC converters ［C］// IEEE 44th ESSCIRC. Dresden, Germany. 2018: 126-129.

[12] [12] LIU D W, HOLLIS S J, STARK B H. A new design technique for sub-nanosecond delay and 200 V/ns power supply slew-tolerant floating voltage level shifters for GaN SMPS ［J］. IEEE Trans Circ Syst I: Regu Pap, 2019, 66(3): 1280-1290.

[13] [13] ZHENG W M, LAM C S, SIN S W, et al. Capacitive floating level shifter:modeling and design ［C］// IEEE Region 10 Conf. Macao, China. 2015: 1-6.