Fig. 1. The block diagram of the 64 GBaud dual channels differential linear TIA chip

Fig. 2. The topology of the TIA stage

Fig. 3. The topology of the VGA stage

Fig. 4. The topology of the CML BUF stage

Fig. 5. The topology of the AGC block

Fig. 6. The topology of the dual independent DCR block

Fig. 7. The topology of the DCOC block

Fig. 8. ICR assembly photo

Fig. 9. ICR S₂₁ curve

Fig. 10. THD@1 GHz