Microelectronics, Volume. 53, Issue 4, 621(2023)

Design of a Clock IP with Wide Power Supply Range

YANG Wenjie... YIN Yongsheng, ZHU Wu and MENG Xu |Show fewer author(s)
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    References(11)

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    [5] [5] XIONG L, WILLSON JR A N. A low-supply PLL with enhanced cascode compensation and a low-supply-sensitivity CCO [C] // Proceed IEEE Custom Integrated Circuits Conference. San Jose, CA, USA. 2010: 1-4.

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    [11] [11] RAZAVI B . Design of CMOS phase-locked loops: from circuit level to architecture level [M]. Cambridge: Cambridge University Press, 2020.

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    YANG Wenjie, YIN Yongsheng, ZHU Wu, MENG Xu. Design of a Clock IP with Wide Power Supply Range[J]. Microelectronics, 2023, 53(4): 621

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    Paper Information

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    Received: Sep. 16, 2022

    Accepted: --

    Published Online: Jan. 3, 2024

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.220362

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