Acta Optica Sinica, Volume. 41, Issue 17, 1704001(2021)
Design and Optimization of Double-Wave-Peak Response CMOS Single-Photon Detector
Figures & Tables(13)
Fig. 8. Schematic and layout patterns of double-wave-peak SPAD. (a) Schematic pattern; (b) layout pattern
Table 1. Comparison of PDP test data between existed SPADs and proposed SPAD
View tableTable 1. Comparison of PDP test data between existed SPADs and proposed SPAD
Device name Process PDP SPAD in Ref. [11] 0.13 μm CMOS 34% (1.7 V@450 nm) SPAD in Ref. [12] a new silicon SPAD process 40% (20 V@800 nm) SPAD in Ref. [13] 0.13 μm CMOS 32%/29% (3 V@450 nm/670 nm) SPAD in Ref. [17] 0.18 μm CMOS 39% (2.5 V@500 nm) Proposed SPAD 0.18 μm BCD 32%/12% (0.5 V@520 nm/840 nm)
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Weiyu Zhang, Yang Wang, Xiangliang Jin. Design and Optimization of Double-Wave-Peak Response CMOS Single-Photon Detector[J]. Acta Optica Sinica, 2021, 41(17): 1704001
Paper Information
Category: Detectors
Received: Feb. 2, 2021
Accepted: Mar. 23, 2021
Published Online: Sep. 3, 2021
The Author Email: Jin Xiangliang (jinxl@hunnu.edu.cn)
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