Acta Photonica Sinica, Volume. 53, Issue 10, 1014002(2024)

Sub-nanosecond Rising-edge Narrow Pulse Driver Circuit and Analog Simulation

Yi LI1...2, Wenlong WEN1,*, Qianhao WANG1, Qianglong LI1, Hualong ZHAO1 and Feng LI1 |Show fewer author(s)
Author Affiliations
  • 1Photonic Manufacturing System and Application Research Center, Xi'an Institute of Optics and Precision Mechanics, Chinese Academy of Sciences, Xi'an 710119, China
  • 2School of Optoelectronics, University of Chinese Academy of Sciences, Beijing 100049, China
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    Figures & Tables(30)
    Circuit systems design
    Gate delay method to generate pulses
    Main charging and discharging circuit design
    Driver circuit for laser diodes
    Temperature and compensation network circuits
    Temperature control circuit schematic
    Temperature control circuit schematic
    Peripheral circuit pulse simulation diagram
    FPGA output pulse width
    Minimum pulse width
    The output repetition frequency of FPGA
    Simulation of Si-based MOSFET and drivers
    Simulation of GaN FET integrated circuits
    Simulated waveforms for capacitance changes
    Simulated waveform of resistance change
    Simulated waveforms for inductance changes
    Simulation of Si-based MOSFET with driver joining transmission characteristics
    Transmission characteristics of conductors
    Introduction of inductive analog leads in the discharge circuit
    Semiconductor laser parallel capacitance
    The output pulse of MOSFET drain
    Semiconductor laser side pulse output
    The output laser pulse of semiconductor laser
    Spectrogram of seed signals
    Power stability test chart
    • Table 1. Electrical characterization of GaN FET integrated circuits

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      Table 1. Electrical characterization of GaN FET integrated circuits

      ParameterTypical
      Peak laser drive current capability15 A
      Maximum gate source voltage5 V
      Input pulldown resistance1.25 kΩ
      Turn on delay time3.5 ns
      Drain rise time0.32 ns
      Turn off delay time3.2 ns
      Drain fall time0.75 ns
      Input capacitance63 pF
      Output capacitance73 pF
    • Table 2. TEC parameters

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      Table 2. TEC parameters

      ParameterTypical
      TEC operating current2.2 A
      TEC operating voltage3.3 V
    • Table 3. Seed source temperature control parameters

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      Table 3. Seed source temperature control parameters

      Temperature/℃Testing thermal resistance/kΩManual thermal resistance/kΩ
      525.3725.40
      1019.8719.90
      1515.8215.71
      2012.5212.49
      259.9810.00
      308.038.06
      356.216.27
    • Table 4. 10 groups of pulse idth values

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      Table 4. 10 groups of pulse idth values

      Number of testsPulse width/ns
      11.054
      21.135
      31.339
      41.413
      51.829
      62.296
      72.858
      83.065
      93.541
      104.540
    • Table 5. Operating parameters of LD

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      Table 5. Operating parameters of LD

      ParameterTypical
      Peak output power700 mW
      Peak output current2.2 A
      Peak wavelength1 064 nm
      Minimum rising edge time1.6 ns
      Peak pulse width500 ns
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    Yi LI, Wenlong WEN, Qianhao WANG, Qianglong LI, Hualong ZHAO, Feng LI. Sub-nanosecond Rising-edge Narrow Pulse Driver Circuit and Analog Simulation[J]. Acta Photonica Sinica, 2024, 53(10): 1014002

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    Paper Information

    Category:

    Received: Mar. 26, 2024

    Accepted: Jun. 18, 2024

    Published Online: Dec. 5, 2024

    The Author Email: WEN Wenlong (romber@opt.ac.cn)

    DOI:10.3788/gzxb20245310.1014002

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