Researching | A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver with 1/4 rate reconfigurable 4-tap FFE and half-rate slicer in a 28-nm CMOS

Journal of Semiconductors, Volume. 45, Issue 6, 062204(2024)

A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver with 1/4 rate reconfigurable 4-tap FFE and half-rate slicer in a 28-nm CMOS

Yukun He, Zhao Yuan, Kanan Wang, Renjie Tang, Yunxiang He, Xian Chen, Zhengyang Ye, and Xiaoyan Gui^*

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School of Microelectronics, Xi’an Jiaotong University, Xi’an 710049, China

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[1] D Kim, M Park, S Jang et al. A 1.1 V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a phase-rotator-based DLL, high-speed SerDes and RX/TX equalization scheme. IEEE International Solid-State Circuits Conference, 380(2019).

[2] Q Pan, X S Luo, Z H Li et al. A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS. J Semicond, 43, 072401(2022).

[5] Q W Liao, Y G Zhang, S Y Ma et al. A 50-Gb/s PAM-4 silicon-photonic transmitter incorporating lumped-segment MZM, distributed CMOS driver, and integrated CDR. IEEE J Solid-State Circuits, 57, 767(2022).

[6] J Lee, P C Chiang, P J Peng et al. Design of 56 gb/s NRZ and PAM4 SerDes transceivers in CMOS technologies. IEEE J Solid-State Circuits, 50, 2061(2015).

[7] J Im, D Freitas, A B Roldan et al. A 40-to-56 Gb/s PAM-4 receiver with ten-tap direct decision-feedback equalization in 16-nm FinFET. IEEE J Solid-State Circuits, 52, 3486(2017).

[8] Y Frans, J Shin, L Zhou et al. A 56-gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16-nm FinFET. IEEE J Solid-State Circuits, 52, 1101(2017).

[9] L K Wang, Y Y Fu, M LaCroix et al. A 64Gb/s PAM-4 transceiver utilizing an adaptive threshold ADC in 16nm FinFET. IEEE International Solid-State Circuits Conference, 110(2018).

[10] N Kocaman, U Singh, B Raghavan et al. An 182mW 1-60Gb/s configurable PAM-4/NRZ transceiver for large scale ASIC integration in 7nm FinFET technology. IEEE International Solid-State Circuits Conference, 120(2022).

[11] P Upadhyaya, C F Poon, S W Lim et al. A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET. IEEE International Solid-State Circuits Conference, 108(2018).

[12] K Gopalakrishnan, A L Ren, A Tan et al. A 40/50/100Gb/s PAM-4 Ethernet transceiver in 28nm CMOS. IEEE International Solid-State Circuits Conference, 62(2016).

[13] E Depaoli, H Y Zhang, M Mazzini et al. A 64 Gb/s low-power transceiver for short-reach PAM-4 electrical links in 28-nm FDSOI CMOS. IEEE J Solid-State Circuits, 54, 6(2019).

[14] P J Peng, J F Li, L Y Chen et al. A 56 Gb/s PAM-4/NRZ transceiver in 40 nm CMOS. IEEE International Solid-State Circuits Conference, 110(2017).

[15] Y K He, Z Yuan, K N Wang et al. A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver in 28-nm CMOS. 2023 IEEE International Conference on Integrated Circuits, Technologies and Applications, 138(2023).

[16] T O Dickson, H A Ainspan, M Meghelli. A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS. IEEE International Solid-State Circuits Conference, 118(2017).

[17] A Roshan-Zamir, O Elhadidy, H W Yang et al. A reconfigurable 16/32 Gb/s dual-mode NRZ/PAM4 SerDes in 65-nm CMOS. IEEE J Solid-State Circuits, 52, 2430(2017).

[18] A Roshan-Zamir, T Iwai, Y H Fan et al. A 56-Gb/s PAM4 receiver with low-overhead techniques for threshold and edge-based DFE FIR- and IIR-tap adaptation in 65-nm CMOS. IEEE J Solid-State Circuits, 54, 672(2019).

[19] J Kim, A Balankutty, R Dokania et al. A 112 Gb/s PAM-4 transmitter with 3-Tap FFE in 10 nm CMOS. IEEE International Solid-State Circuits Conference, 102(2018).

[20] C Menolfi, M Braendli, P A Francese et al. A 112 Gb/S 2.6 pJ/b 8-tap FFE PAM-4 SST TX in 14 nm CMOS. IEEE International Solid-State Circuits Conference, 104(2018).

[21] B Razavi. Jitter-power trade-offs in PLLs. IEEE Transactions on Circuits and Systems I, 68, 1381(2021).

[22] Z Toprak-Deniz, J E Proesel, J F Bulzacchelli et al. A 128Gb/s 1.3pJ/b PAM-4 transmitter with reconfigurable 3-tap FFE in 14nm CMOS. 2019 IEEE International Solid-State Circuits Conference, 122(2019).

[23] Y T Lin, W Z Chen. A 50 Gb/s PAM-4 transmitter with feedforward equalizer and background phase error calibration. IEEE Asian Solid-State Circuits Conference, 1(2020).

[24] R J Tang, Z Yuan, Y Y Lv et al. A continuous-time linear equalizer with ultrafine gain adjustment achieving 0.3-dB DC-gain step and 0.9-dB peaking-gain step. IEEE Microw Wirel Technol Lett, 33, 559(2023).

[25] K C Chen, W W T Kuo, A Emami. A 60-gb/s PAM4 wireline receiver with 2-tap direct decision feedback equalization employing track-and-regenerate slicers in 28-nm CMOS. IEEE J Solid-State Circuits, 56, 750(2021).

[26] S Yeom, T Sim, J Han. An analysis of CMOS latched comparators. International Conference on Electronics, Information, and Communication, 1(2023).

[27] R Günay, S Ergün. IC random number generator exploiting two simultaneous metastable events of tetrahedral oscillators. IEEE Trans Circuits Syst II Express Briefs, 67, 1634(2020).

[28] R L Smith, T H Lee. Analysis and design of a tetrahedral oscillator. IEEE Trans Circuits Syst II Express Briefs, 69, 75(2022).

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Yukun He, Zhao Yuan, Kanan Wang, Renjie Tang, Yunxiang He, Xian Chen, Zhengyang Ye, Xiaoyan Gui. A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver with 1/4 rate reconfigurable 4-tap FFE and half-rate slicer in a 28-nm CMOS[J]. Journal of Semiconductors, 2024, 45(6): 062204

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Paper Information

Category: Articles

Received: Jan. 12, 2024

Accepted: --

Published Online: Jul. 8, 2024

The Author Email: Gui Xiaoyan (XYGui)

DOI:10.1088/1674-4926/24010001

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