Researching | Emerging trends of integrated-mixed-signal chips in ISSCC 2023

Journal of Semiconductors, Volume. 44, Issue 5, 050204(2023)

Emerging trends of integrated-mixed-signal chips in ISSCC 2023

Jinbo Chen^*, Jie Yang^*, and Mohamad Sawan^**

Author Affiliations

CenBRAIN Neurotech, School of Engineering, Westlake University, Hangzhou 310024, China

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References(13)

[1] M Verhelst, A Bahai. Where analog meets digital: Analog-to-information conversion and beyond. IEEE Solid-state circuits magazine, 7, 67(2015).

[2] C H Chan, L Cheng, W Deng et al. Trending IC design directions in 2022. J Semicond, 43, 071401(2022).

[3] D Bankman, L Yang, B Moons et al. An Always-On 3.8 μJ/86% CIFAR-10 mixed-signal binary CNN processor with all memory on chip in 28-nm CMOS. IEEE Journal of Solid-State Circuits, 54, 158(2018).

[4] R B Staszewski, I Bashir, E Blokhina et al. Cryo-CMOS for quantum system on-chip integration: Quantum computing as the development driver. IEEE Solid-State Circuits Magazine, 13, 46-53(2021).

[5] P C Wu, J W Su, L Y Hong et al. A 22nm 832Kb hybrid-domain floating-point SRAM in-memory-compute macro with 16.2-70.2 TFLOPS/W for high-accuracy AI-edge devices. 2023 IEEE International Solid-State Circuits Conference (ISSCC), 126(2023).

[6] A M A Ali, H Dinc, P Bhoraskar et al. A 12-b 18-GS/s RF sampling ADC with an integrated wideband track-and-hold amplifier and background calibration. IEEE Journal of Solid-State Circuits, 55, 3210(2020).

[8] T Seol, S Lee, G Kim et al. A 1V 136.6 dB-DR 4kHz-BW ΔΣ current-to-cigital converter with a truncation-noise-shaped baseline-servo-loop in 0.18μm CMOS. 2023 IEEE International Solid-State Circuits Conference (ISSCC), 482(2023).

[9] G Kim, S Lee, T Seol et al. 32.4 A 1V-supply 1.85Vpp-input-range 1kHz-BW 181.9 dB-FOM DR 179.4 dB-FOM SNDR 2nd-order noise-shaping SAR-ADC with enhanced input impedance in 0.18μm CMOS. 2023 IEEE International Solid-State Circuits Conference (ISSCC), 484(2023).

[10] J Xu, J Sales Filho, S Nag et al. Fascicle-selective bidirectional peripheral nerve interface IC with 173dB FOM noise-shaping SAR ADCs and 1.38pJ/b frequency-multiplying current-ripple radio transmitter. 2023 IEEE International Solid-State Circuits Conference (ISSCC), 31(2023).

[11] C Mu, J P Zheng, C X Chen. Beyond convolutional neural networks computing: New trends on ISSCC 2023 machine learning chips. J Semicond, 44, 050203(2023).

[12] B Munger, K Wilcox, J Sniderman et al. “Zen 4”: The AMD 5nm 5.7 GHz x86-64 microprocessor core. 2023 IEEE International Solid-State Circuits Conference (ISSCC), 38(2023).

[13] K Seong, D Park, G Bae et al. A 4nm 32Gb/s 8Tb/s/mm die-to-die chiplet using NRZ single-ended transceiver with equalization schemes and training techniques. 2023 IEEE International Solid-State Circuits Conference (ISSCC), 114(2023).

[14] F Tu, Y Wang, Z Wu et al. 16.4 TensorCIM: A 28nm 3.7 nJ/Gather and 8.3 TFLOPS/W FP32 Digital-CIM tensor processor for MCM-CIM-based beyond-NN acceleration. 2023 IEEE International Solid-State Circuits Conference (ISSCC), 254(2023).

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Jinbo Chen, Jie Yang, Mohamad Sawan. Emerging trends of integrated-mixed-signal chips in ISSCC 2023[J]. Journal of Semiconductors, 2023, 44(5): 050204

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Paper Information

Category: Articles

Received: Apr. 25, 2023

Accepted: --

Published Online: Jun. 15, 2023

The Author Email: Chen Jinbo (yangjie@westlake.edu.cn), Yang Jie (yangjie@westlake.edu.cn), Sawan Mohamad (sawan@westlake.edu.cn)

DOI:10.1088/1674-4926/44/5/050204

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