Microelectronics, Volume. 54, Issue 2, 201(2024)

Low-Noise Analog Front-End Circuit Design for 80 Gbit/s PAM4 Signal Optical Receiver

ZHANG Chunming... WANG Hao and SONG Ruxue |Show fewer author(s)
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    References(13)

    [1] [1] DANESHGAR S, LI H, KIM T, et al. a 128 Gb/s PAM4 linear TIA with 12.6 pA/sqrt(Hz) noise density in 22 nm FinFET CMOS [C] // 2021 IEEE Radio Frequency Integrated Circuits Symposium(RFIC). Atlanta, GA, USA. 2021: 135-138.

    [2] [2] LI H, BALAMURUGAN G, JAUSSI J, et al. A 112Gb/s PAM4 linear TIA with 0.96 pJ/bit energy efficiency in 28 nm CMOS [C] // 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC).Gresden, Germany.2018: 238-241.

    [3] [3] LAKSHMIKUMAR K R, KURYLAK A,NAGARAJU M, et al. A process and temperature insensitive CMOS linear TIA for 100 Gb/s/λ PAM-4 optical links [J]. IEEE Journal of Solid-State Circuits,2019, 54(11): 3180-3190.

    [4] [4] YU K, LI C, HUANG T C, et al. 56 Gb/s PAM-4 optical receiver frontend in an advanced Fin FET process [C] // 2015 IEEE 58th International Midwest Symposium on circuits and systems (MWSCAS). Fort Collins, CO, USA.2015: 1-4.

    [5] [5] FU K L, LIU S I. A 56 Gbps PAM-4 optical receiver front-end [C] // 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC). Seoul,Korea(South).2017:77-80.

    [6] [6] ZHENG K, FRANS Y, CHANG K, et al. A 56 Gb/s 6 mW 300 μm2 inverter-based CTLE for short-reach PAM2 applications in 16 nm CMOS [C] // 2018 IEEE Custom Integrated Circuits Conference (CICC). San Diego, CA, USA.2018: 1-4.

    [7] [7] ZHENG K, FRANS Y, AMBATIPUDI S L, et al.An inverter-based analog front-end for a 56-Gb/s PAM-4 wireline transceiver in 16-nm CMOS [J].IEEE Solid-State Circuits Letters, 2018, 1(12): 249-252.

    [8] [8] OZKAYA I, CEVRERO A, FRANCESE P A, et al.A 64-Gb/s 1.4-pJ/b NRZ optical receiver data-path in 14-nm CMOS FinFET [J]. IEEE Journal of Solid-State Circuits, 2017, 52(12): 3458-3473.

    [9] [9] LI D, MINOIA G, REPOSSI M, et al. A low-noise design technique for high-speed CMOS optical receivers[J]. IEEE Journal of Solid-State Circuits, 2014, 49(6): 1437-1447.

    [10] [10] WANG J C, PAN Q, QIN Y J, et al. A fully integrated 25 Gb/s low-noise TIA + CDR optical receiver designed in 40-nm-CMOS [C] // 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC).Tainan, China. 2018.

    [11] [11] WU X, ZHAO Z L, WU C N, et al. Design of analog frontend circuit for 40 Gb/s high speed serial interface receiver [J]. Microelectronics and Computers, 2022,39(2): 114-120.

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    ZHANG Chunming, WANG Hao, SONG Ruxue. Low-Noise Analog Front-End Circuit Design for 80 Gbit/s PAM4 Signal Optical Receiver[J]. Microelectronics, 2024, 54(2): 201

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    Paper Information

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    Received: Aug. 4, 2023

    Accepted: --

    Published Online: Aug. 21, 2024

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.230292

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