Microelectronics, Volume. 54, Issue 2, 201(2024)

Low-Noise Analog Front-End Circuit Design for 80 Gbit/s PAM4 Signal Optical Receiver

ZHANG Chunming... WANG Hao and SONG Ruxue |Show fewer author(s)
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    A low-noise analog front-end circuit (AFE) was designed using UMC 28 nm CMOS technology for optical receivers operating at 80 Gbit/s PAM4. To address the tradeoff between the noise and bandwidth, we adopted a trans-impedance amplifier (TIA) cascaded continuous time linear equalizer (CTLE) and input inductor peaking. A VGA with trans-conductance and a trans-impedance (gm-TIA) structure was adopted to effectively control the low-frequency gain and further expand the bandwidth. The circuit achieves a trans-impedance gain of 48.5 dBΩ, a bandwidth of 36.1 GHz, an average equivalent input current noise of 22.6 pA/ Hz, and a power consumption of 14.5 mW, under the conditions of an input capacitance of 100 fF and a supply voltage of 1.2 V.

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    ZHANG Chunming, WANG Hao, SONG Ruxue. Low-Noise Analog Front-End Circuit Design for 80 Gbit/s PAM4 Signal Optical Receiver[J]. Microelectronics, 2024, 54(2): 201

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    Paper Information

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    Received: Aug. 4, 2023

    Accepted: --

    Published Online: Aug. 21, 2024

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.230292

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