Fig. 1. Structure of SFD circuit

Fig. 2. Circuit block diagram

Fig. 3. Structure of analog circuit

Fig. 4. Structure of OTA

Fig. 5. Analog signal chain and current bias diagram

Fig. 6. Structure of current bias

Fig. 7. Layout of corecell circuit

Fig. 8. Controlling time series of simulation(NDR=0)

Fig. 9. Controlling time series of simulation(NDR=1)

Fig. 10. Structure of SR latch

Fig. 11. Structure of NDR circuit 1

Fig. 12. Simulation result of NET1

Fig. 13. Structure of NDR circuit 2

Fig. 14. Simulation result of NET3

Fig. 15. Simulation result of INTRST(NDR=0)

Fig. 16. Simulation result of INTRST(NDR=1)

Fig. 17. Diagram of non-destructive readout function

Fig. 18. Relationship diagram between signal and time

Fig. 19. Relationship between output voltage and photocurrent

Fig. 20. Sample picture of IRFPA

Fig. 21. Test system of long integration time

Fig. 22. Average voltage of FPA vs integration time

Fig. 23. Dark current of 640×512 IRFPA

Fig. 24. Test results of dark current

Fig. 25. Dark current under different power consumption

Fig. 26. Dark current under different power consumption

Fig. 27. Signal voltage vs integration time

Fig. 28. Test result of circuit noise (5 fF)