Microelectronics, Volume. 53, Issue 4, 574(2023)

Research on Optimal Design Algorithm of Incremental Σ-Δ Modulator

WANG Wei1... MA Li1, CHIO U-Fat1, LI Mingbo1, LIU Binzheng1, SHUI Shaolin1, LUO Chenbin1 and YUAN Jun2 |Show fewer author(s)
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  • 1[in Chinese]
  • 2[in Chinese]
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    References(14)

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    [2] [2] TAN Z, CHEN C H, CHAE Y, et al. Incremental delta-sigma ADCs: a tutorial review [J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, 67(12): 1-13.

    [3] [3] FREITAS L C, MORGADODIAS F. Reference power supply connection scheme for low-power CMOS image sensors based on incremental sigma-delta converters [J]. Electronics, 2021, 10(3): 299.

    [4] [4] LEE S , JEONG J , KIM T, et al. A 52-Mpixel 884-dB DR 12-in CMOS X-ray detector with 16-bit column-parallel continuous-time incremental ΔΣ ADCs [J]. IEEE Journal of Solid-State Circuits, 2020, 55(11): 2878-2888.

    [5] [5] QUIQUEMPOIX V, DEVAL P, BARRETO A, et al. A low-power 22-bit incremental ADC [J]. IEEE Journal of Solid-State Circuits, 2006, 41(7): 1562-1571.

    [6] [6] SHIN M S. A 192-Megapixel CMOS image sensor with column-parallel low-power and area-efficient SA-ADCs [J]. IEEE Transactions on Electron Devices, 2012, 59(6): 1693-1700.

    [7] [7] MARKUS J, SILVA J, TEMES G C. Design theory for high-order incremental converters [C] // IEEE International Symposium on Intelligent Signal Processing. Budapest, Hungary. 2003: 3-8.

    [8] [8] MARKUS J, SILVA J, TEMES G C. Theory and applications of incremental delta-sigma converters [J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2004, 51(4): 678-690.

    [9] [9] SCHREIER R, PAVAN S, TEMES G C. Understanding delta-sigma data converters // incremental analog-to-digital converters [M]. Hoboken, New Jersey: Willey Press, 2017: 407-422.

    [10] [10] SHIM J B, KIM M K, HONG O K, et al. An ultra-low-power 16-bit second-order incremental ADC with SAR-based integrator for IoT sensor applications [J]. IEEE Transactions on Circuits & Systems II: Express Briefs, 2018, 67(10): 1685-1689.

    [11] [11] OH B, KIM J J. A four-step incremental ADC based on double extended binary counting with capacitive DAC [J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2019, 65(12): 1899-1903.

    [12] [12] AKBARI M, HONARPARVAR M, SAVARIA Y, et al. Power bound analysis of a two-step MASH incremental ADC based on noise-shaping SAR ADCs [J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2021, 68(8): 3133-3146.

    [13] [13] ZHANG Y, CHEN C H, HE T, et al. A 16 b multi-step incremental analog-to-digital converter with single-opamp multi-slope extended counting [J]. IEEE Journal of Solid-State Circuits, 2017, 52(4): 1066-1076.

    [14] [14] CHEN C H, ZHANG Y, HE T, et al. A micro-power two-step incremental analog-to-digital converter [J]. IEEE Journal of Solid State Circuits, 2015, 50(8): 1796-1808.

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    WANG Wei, MA Li, CHIO U-Fat, LI Mingbo, LIU Binzheng, SHUI Shaolin, LUO Chenbin, YUAN Jun. Research on Optimal Design Algorithm of Incremental Σ-Δ Modulator[J]. Microelectronics, 2023, 53(4): 574

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    Paper Information

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    Received: Nov. 18, 2022

    Accepted: --

    Published Online: Jan. 3, 2024

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.220466

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