Fig. 1. 15 μm 1280×1024 cooled infrared imaging components. (a) Schematic diagram; (b) Exploded view

Fig. 2. Image processing circuit hardware design

Fig. 3. Detector bias voltage circuit

Fig. 4. Low noise circuit design scheme

Fig. 5. Power circuit diagram

Fig. 6. Design diagram of FPGA₁ processing circuit program module

Fig. 7. Design diagram of FPGA₂ enhancement board program module

Fig. 8. Multi-point correction temperature point selection diagram

Fig. 9. Multi-point calibration temperature selection. (a) Average segmentation; (b) Adaptive segmentation

Fig. 10. 15 μm 1280 × 1024 cooled infrared imaging components

Fig. 11. RMS value of the noise floor of the measurement circuit

Fig. 12. Noise spectrum curve of output voltage V₄

Fig. 13. NETD test picture

Fig. 14. High and low temperature imaging images. (a) −40 ℃; (b) 60 ℃

Fig. 15. Block inhibition implementation effect diagram. (a) Before processing; (b) After processing

Fig. 16. CLAHE implementation effect diagram. (a) Traditional CLAHE; (b) Optimized CLAHE

Fig. 17. Digital detector imaging picture. (a) Traditional; (b) Optimized