Experiment Science and Technology, Volume. 22, Issue 5, 28(2024)
Digital Clock Circuit Design Based on Vivado and Nexys4 DDR
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Table 1. [in Chinese]
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变量 clk reset sppedctrl out_led aud_pwm aud_sd clk_refresh Nexys4 DDR 板上的引脚 CLK E3 BTNC M18 SW0~SW3 J15、L16、M13、R15 LED0 H17 AUD_PWM A11 AUD_SD D12 LED1 J13 变量 seg_sel oDisplay Nexys4 DDR 板上的引脚 AN0~AN7 J17、J18、T9、J14、P14、T14、K2、U13 CA~CG T10、R10、K16、K13、P15、T11、L18
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Dian ZHANG, Qiaochu XIONG. Digital Clock Circuit Design Based on Vivado and Nexys4 DDR[J]. Experiment Science and Technology, 2024, 22(5): 28
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Received: Apr. 12, 2023
Accepted: --
Published Online: Dec. 13, 2024
The Author Email: XIONG Qiaochu (熊翘楚)
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