[2] [2] CESCHIA M. VIOLANTE M. REORDA M S. et al.Identification and classification of single-event upsets in the configuration memory of SRAM-based FPGAs［J］.IEEE Transactions on Nuclear Science. 2003. 50(6):2088-2094.

[4] [4] STERPONE L. VIOLANTE M.A new analytical approach to estimate the effects of SEUs in TMR architectures implemented through SRAM-based FPGAs［J］.IEEE Tran-sactions on Nuclear Science. 2005. 52(6):2217-2223.

[5] [5] BARAZA J C. GRACIA J. BLANC S. et al.Enhancement of fault injection techniques based on the modification of VHDL code［J］.IEEE Transactions on Very Large Scale Integration Systems. 2008. 16(6):693-706.

[6] [6] ALDERIGHI M. D'ANGELO S. MANCINI M. et al.A fault injection tool for SRAM-based FPGAs［C］//The 9th International On-Line Testing Symposium. IEEE. 2003:129-133.

[7] [7] ZHANG R S. XIAO L Y. LI J.A fast and accurate fault injection platform for SRAM-based FPGAs［C］//The 12th International Conference on ASIC. IEEE. 2017:435-438.

[9] [9] Aeronautical Radio Inc.Aircraft data network-Part 7:Avionics full-duplex switched Ethernet network［S］.［S.l.］ARINC. 2005.