Fig. 1. The structure of pulse frequency modulation digital readout circuit with CTIA input stage

Fig. 2. The non-ideal reset of pulse frequency modulation digital readout circuit with CTIA input stage

Fig. 3. The timing diagram of two-step residual-time-counting pulse frequency modulation digital readout circuit

Fig. 4. The circuit diagram of complementary self-biased differential comparator

Fig. 5. The simulation results of two-step residual-time-counting pulse frequency modulation digital readout circuit

Fig. 6. The unit layout of two-step residual-time-counting pulse frequency modulation digital readout circuit