Microelectronics, Volume. 53, Issue 4, 588(2023)

Design of a CMOS Millimeter-Wave Low-Phase-Noise Cascaded Dual Phase-Locked Loop Frequency Synthesizer

YIN Shiwei1... ZHANG Changchun1,2, TANG Lu2 and YUAN Hengzhou3 |Show fewer author(s)
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
  • 3[in Chinese]
  • show less
    References(11)

    [1] [1] CHAN C H, CHENG L, DENG W, et al. Trending IC design directions in 2022 [J]. Journal of Semiconductors, 2022, 43(7): 8-54.

    [2] [2] RICHARD O, SILIGARIS A, BADETS F, et al. A 175 to 2094 GHz and 35 to 4188 GHz PLL in 65 nm CMOS for wireless HD applications [C] // IEEE ISSCC. San Francisco, CA, USA. 2010: 252-253.

    [3] [3] GAO X, KLUMPERINK E, BOHSALI M, et al. A low noise sub-sampling PLL in which divider noise is eliminated and PD/CP noise is not multiplied by N2 [J]. IEEE Journal of Solid-State Circuits, 2009, 44(12): 3253-3263.

    [4] [4] MARKULIC N, RENUKASWAMY P T, MARTENS E, et al. A 55 GHz background calibrated sub-sampling polar transmitter with 413 dB EVM at 1024 QAM in 28 nm CMOS [J]. IEEE Journal of Solid-State Circuits, 2019, 54(4): 1059-1073.

    [5] [5] LIAO D, ZHANG Y, DAI F, et al. An mm-wave synthesizer with robust locking reference-sampling PLL and wide range injection locked VCO [J]. IEEE Journal of Solid-State Circuits, 2020, 55(3): 536-546.

    [6] [6] EL-HALWAGY W, NAG A, HISAYASU P, et al. A 28 GHz quadrature fractional-N frequency synthesizer for 5G transceivers with less than 100-fs jitter based on cascaded PLL architecture [J]. IEEE Transactions on Microwave Theory & Techniques, 2017, 65(2): 396-413.

    [7] [7] HSU C M, STRAAYER M Z, PERROTT M H. A low-noise wide BW 36 GHz digital ΔΣ fractional-N frequency synthesizer with a noise shaping time to digital converter and quantization noise cancellation [C] // IEEE ISSCC. San Francisco, CA, USA. 2008.

    [8] [8] STRAAYER M Z, PERROTT M H. A multi-path gated ring oscillator TDC with first-order noise shaping [C] // IEEE ISSCC. San Francisco, CA, USA. 2009.

    [9] [9] HEKMAT M, ARYANFAR F, WEI J, et al. A 25 GHz fast-lock digital LC PLL with multi-phase output using a magnetically-coupled loop of oscillators [J]. IEEE Journal of Solid-State Circuits, 2015, 50(2): 490-502.

    [11] [11] YOON H, KIM J, PARK S, et al. A 31 dBc integrated phase noise 29 GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward compatible 5G using a frequency doubler and injection locked frequency multipliers [C] //IEEE ISSCC. San Francisco, CA, USA. 2018.

    [12] [12] SHEN Z, JIANG H, YANG F, et al. A 24 GHz self-calibrated ADPLL based FMCW synthesizer with 001% rms frequency error under 32 GHz chirp bandwidth and 320 MHz/μs slope [C] // IEEE ISSCC. San Francisco, CA, USA. 2021.

    Tools

    Get Citation

    Copy Citation Text

    YIN Shiwei, ZHANG Changchun, TANG Lu, YUAN Hengzhou. Design of a CMOS Millimeter-Wave Low-Phase-Noise Cascaded Dual Phase-Locked Loop Frequency Synthesizer[J]. Microelectronics, 2023, 53(4): 588

    Download Citation

    EndNote(RIS)BibTexPlain Text
    Save article for my favorites
    Paper Information

    Category:

    Received: Oct. 23, 2022

    Accepted: --

    Published Online: Jan. 3, 2024

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.220424

    Topics