In last few decades, GaN power high-electron-mobility transistors (HEMTs) have become an indispensable core component of power electronics, owing to their high breakdown voltage and fast switching speed^[1−6]. To further enhance the reliability and speed of the device, monolithically integrated GaN-based peripheral circuits composed of logic modules that serve as the driving, control, sensing and protection units, are highly desirable. One of the promising technologies, especially for high-temperature operation application, is the GaN-based CMOS platform, which delivers extremely low power consumption^[7]. The key issue of GaN-based CMOS technology is the low current density of the GaN p-FETs, which ascribe to the high activation energy (~170 meV) of Mg doping, low hole mobility and the difficulty in forming ohmic contact due to the p-GaN deep valance bands^[8−10]. To improve the conduction characteristic of the GaN p-channel device, polarization-enhanced epitaxy technology was adopted to induce high-density two-dimensional hole gas (2DHG), which can effectively increase carrier concentration^[11−14]. At the same time, in order to achieve the enhancement mode (E-mode), a partial recessed p-GaN channel in the gate region is needed^[15−22].

As the core component of the pull-up device in GaN-based CMOS logic circuit topology, the p-FETs with a low subthreshold slope (SS) are beneficial for achieving lower power consumption of the logic circuit due to the operating voltage reduction^[23]. A high-k gate dielectric is a facile method that reduces the SS of the devices. Among all the high-k dielectrics, HfO₂ is favorable due to its large dielectric constant (~25) and perfect compatibility with CMOS fabrication processes^[24]. Therefore, HfO₂ is selected as the high-k dielectric material for our fabricated GaN p-FETs.

In this work, E-mode GaN p-FETs with O₃-Al₂O₃/HfO₂-stacked gate dielectric are fabricated on a p⁺⁺-GaN/p-GaN/AlN/AlGaN/AlN/GaN heterostructure grown on a Si substrate. The O₃-Al₂O₃ insertion layer effectively improves the voltage blocking of the stack dielectric and reduces the leakage current. Meanwhile, the introduction of HfO₂ reduces the SS of GaN p-FETs from 161 mV/dec to 107 mV/dec, which significantly improves the current performance of the GaN p-FETs. The improved subthreshold performance of the p-FETs enables high ON-OFF current ratio with low operating voltage, which is beneficial for reducing the power consumption of GaN-based CMOS logic driver circuits.

Fig. 1(a) shows the cross-sectional schematic of the fabricated metal–oxide–semiconductor (MOS) device for dielectric leakage characterization. The employed p⁺⁺-GaN/p-GaN/AlN/AlGaN/AlN/GaN heterostructure was grown by metal–organic chemical vapor deposition (MOCVD) on the Si substrate. It consists of a ~10-nm p⁺⁺-GaN capping layer (Mg: 2 × 10²⁰ cm⁻³), a ~85-nm p-GaN layer (Mg: (4–6) × 10¹⁹ cm⁻³), a ~2-nm AlN polarization enhancement layer, a ~3-nm Al_0.25Ga_0.75N ultrathin barrier layer (UTB), a ~1-nm AlN interface enhancement layer, a 300-nm unintentionally doped GaN n-channel layer and a 3.6-µm (Al)GaN high-resistivity buffer layer with C doping. The 3-nm UTB-Al_0.25Ga_0.75N layer is intended for a AlGaN-recess-free E-mode n-FETs for p/n-FETs integration^[25]. The hole sheet density and mobility were measured to be 2.3 × 10¹³ cm⁻² and 11.5 cm²/(V·s) respectively by Van der Pauw Hall measurement. The gate dielectrics for comparison are a 20-nm HfO₂, 20-nm O₃-Al₂O₃ and an O₃-Al₂O₃/HfO₂ (5/15 nm) stack, both of which are grown by atomic layer deposition (ALD).

The leakage characteristic of different dielectrics is shown in Fig. 1(b). The 20-nm HfO₂ shows a lower breakdown voltage and higher leakage current density than that of the 20-nm O₃-Al₂O₃ due to its lower band gap (HfO₂: ~5.8 eV, O₃-Al₂O₃: ~7.1 eV) and valence band offset from p-GaN (p-GaN/HfO₂: ~0.3 eV, p-GaN/O₃-Al₂O₃: ~1.7 eV)^{[26, 27]}. The introduction of the 5-nm O₃-Al₂O₃ insertion layer can effectively reduce the leakage of the O₃-Al₂O₃/HfO₂ stack and improve its voltage-blocking capability.

Fig. 2(a) exhibits the cross-sectional schematic of the fabricated E-mode GaN p-FETs. Device fabrication commenced with source/drain definition by photolithography, followed by Ni/Au (50/100 nm) metal stack evaporation. Rapid thermal annealing (RTA) in the air environment at 550 °C for 60 s was performed after lift-off. Thanks to the p⁺⁺-GaN capping layer, linear I−V curves were obtained. The contact resistance (R_c) of 18.86 Ω·mm (ρ_c = 1.34 × 10⁻⁴ Ω·cm²) and sheet resistance (R_sh) of 2.65 × 10⁴ Ω/sq are determined by the transfer length method (TLM) respectively, as shown in Fig. 2(b). Fig. 2(c) benchmarks the R_c and hole sheet density of the heterostructure used in this work with other similar Ⅲ-nitride heterostructures. The low R_c achieved is comparable to state-of-the-art results.

The mesa isolation was implemented by the Cl₂/BCl₃-based inductively coupled plasma-reactive ion etching (ICP-RIE) process to the GaN buffer. A two-step gate etching process was adopted to overcome the decreased OFF-state blocking voltage associated with the p⁺⁺-GaN capping layer^[28]. The remaining p-GaN under the central gate trench is 8 nm as confirmed by atomic force microscopy (AFM), as shown in Fig. 2(d). The two-step gate trench was then subjected to an UV/O₃ treatment at 100 °C for 30 min. Prior to the deposition of the gate dielectric, in-situ remote plasma pretreatments (RPP)^[29] by using NH₃/N₂ plasmas applied were conducted. After the source/drain region opening, the GaN p-FET fabrication was completed with an evaporated Ni/Au (40/400 nm) metal stack as the gate metal and probing pad. For comparison, the devices using the 20-nm O₃-Al₂O₃ and the O₃-Al₂O₃/HfO₂ (5/15 nm) stack as the gate dielectric are both fabricated. The fabricated GaN p-FETs possess a gate length (L_G) of 2 μm, an equivalent gate to source length (L_GS) and a gate to drain length (L_GD) of 5 μm.

Fig. 3(a) shows DC transfer characteristics of the fabricated GaN p-FETs with an O₃-Al₂O₃ and O₃-Al₂O₃/HfO₂ stack as the gate dielectric at V_DS of –1 V. Since the 8-nm p-GaN layer only remained at the bottom of the gate trench featuring the weakening of the built-in polarization, both of the devices behave as E-modes and exhibit a high I_ON/I_OFF ratio of 6 × 10⁶. Thanks to the high-quality O₃-Al₂O₃ insertion layer, the device with the O₃-Al₂O₃/HfO₂ gate stack shows a low gate leakage below 10⁻⁶ mA/mm, the same as the device with 20-nm O₃-Al₂O₃ gate dielectric. In addition, a steeper transfer curve is obtained due to the high dielectric constant of HfO₂ for the GaN p-FET with the O₃-Al₂O₃/HfO₂ gate stack. Its minimum SS is extracted to be 107 mV/dec, which is significantly lower than the 161 mV/dec of the comparison device (see Fig. 3(b)).

Fig. 4(a) depicts the output curves of the devices. Owing to the p⁺⁺-GaN cap layer of the epitaxial structure, an offset voltage, which is usually observed in I_DS−V_DS curves of p-FETs fabricated on the moderate Mg-doped p-GaN layer^{[31, 32]}, is effectively eliminated. The O₃-Al₂O₃/HfO₂-stacked device with better channel modulation capability delivers a high-saturation current density of −4.9 mA/mm and an on-resistance (R_on) of 0.70 kΩ·mm at V_GS = −10 V. Three-terminal OFF-state characteristics of the fabricated GaN p-FET is plotted in Fig. 4(b). A destructive hard breakdown was observed at −52 and −61 V on the devices with the O₃-Al₂O₃/HfO₂ gate stack and the O₃-Al₂O₃ gate dielectric, respectively.

Table 1 benchmarks the fabricated GaN p-FETs in this work with some other reported GaN p-FETs. Our E-mode GaN p-FETs exhibit high I_ON/I_OFF ratio and low SS.

The scaling effect on the gate length of the GaN p-FETs was also studied. Much higher |I_D,max| and lower R_on are obtained (Fig. 5). By optimizing the size of the devices or directly using self-alignment structure^{[16, 17]}, the current density of GaN p-FETs will be further improved.

In this work, the leakage characteristic of O₃-Al₂O₃ and HfO₂ is investigated on the p-channel GaN device platform. The introduction of the O₃-Al₂O₃ insertion layer can effectively reduce the leakage and increase the breakdown voltage of the O₃-Al₂O₃/HfO₂ stack. E-mode GaN p-FETs with an O₃-Al₂O₃/HfO₂ gate stack were fabricated on the p⁺⁺-GaN/p-GaN/AlN/AlGaN/AlN/GaN/Si heterostructure. The fabricated GaN p-FETs possess a high current density of −4.9 mA/mm, a high I_ON/I_OFF ratio of 6 × 10⁶ and a low SS of 107 mV/dec, which are promising for applications in GaN CMOS logic platforms.