Microelectronics, Volume. 53, Issue 1, 95(2023)
A Two-Stage CDS Circuit for Eliminating FPN in Analog TOF Array Detector
[1] [1] KUMAGAI O, OHMACHI J, MATSUMURA M, et al. A 189×600 back-illuminated stacked SPAD direct time-of-flight depth sensor for automotive LiDAR systems [C] // IEEE Int Sol Sta Circ Conf. Francisco, CA, USA. 2021: 110-112.
[2] [2] SEO H, YOON H, KIMET D, et al. Direct TOF scanning LiDAR sensor with two-step multievent histogramming TDC and embedded interference filter [J]. IEEE J Sol Sta Circ, 2021, 56(4): 1022-1035.
[3] [3] MA Z Q, WU Z, XU Y. Compact SPAD pixels with fast and accurate photon counting in the analog domain [J]. J Semicond, 2021, 42(5): 052402.
[4] [4] MORRISON D, KENNEDY S, DELIC D, et al. A 64 × 64 SPAD flash LIDAR sensor using a triple integration timing technique with 1.95 mm depth resolution [J]. IEEE Sensors J, 2021, 21(10): 11361-11373.
[5] [5] XIMENES A R, PADMANABHAN P, LEE M, et al. A 256×256 45/65 nm 3D-stacked SPAD-based direct TOF image sensor for LiDAR applications with optical polar modulation for up to 18.6 dB interference suppression [C] // IEEE Int Sol Sta Circ Conf. Francisco, CA, USA. 2018: 96-98.
[6] [6] YI I M, MIURA N, NOSAKA H. A 4-GS/s 11.3-mW 7-bit time-based ADC with folding voltage-to-time converter and pipelined TDC in 65-nm CMOS [J]. IEEE J Sol Sta Circ, 2021, 56(2): 465-475.
[8] [8] ACCONCIA G, GHIONI M, RECH I. 4.3 ps RMS jitter time to amplitude converter in 350 nm Si-Ge technology [C] // 7th Int Conf on EBCCSP. Krakow, Poland. 2021: 1-4.
[11] [11] TAKAHASHI T, KAJI Y, TSUKUDA Y, et al. A stacked CMOS image sensor with array-parallel ADC architecture [J]. IEEE J Sol Sta Circ, 2018, 53(4): 1061-1070.
[12] [12] PARK K, YEOM S, YIM S Y. Ultra-low power CMOS image sensor with two-step logical shift algorithm-based correlated double sampling scheme [J]. IEEE Trans Circ Syst I: Regu Pap, 2020, 67(11): 3718-3727.
[13] [13] BRODERSEN R W, EMMONS S P. Noise in buried channel charge-coupled device [J]. IEEE J Sol Sta Circ, 1976, 11(1): 147-155.
[14] [14] LU B, CHEN Y. Design of a CDS ASIC for multireadout X-Ray CCDs with a 0.032% INL [J]. IEEE Trans Nucl Sci, 2018, 65(6): 1307-1314.
[15] [15] HAN S W, YOON E. Area-efficient correlated double sampling scheme with single sampling capacitor for CMOS image sensors [J]. Elec Lett, 2006, 42(6): 335-337.
[17] [17] PERENZONI M, MASSARI N, STOPPA D, et al. A 160×120-pixels range camera with on-pixel correlated double sampling and nonuniformity correction in 29.1 μm pitch [C] // Proceed ESSCIRC. Seville, Spain. 2010: 294-297.
[18] [18] SOUZA R A, VENTURA L G M, REIS L P, et al. CMOS image sensor with FPN reduction by correlated double sampling in current mode [C] // 31st SBMicro. Belo Horizonte, Brazil. 2016: 1-4.
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LIU Zhiqiang, DONG Jie, MA Zhiqiang, ZHU Sihui, XU Yue. A Two-Stage CDS Circuit for Eliminating FPN in Analog TOF Array Detector[J]. Microelectronics, 2023, 53(1): 95
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Received: Mar. 14, 2022
Accepted: --
Published Online: Dec. 15, 2023
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