Fig. 1. Overall design of digital delay and pulse generator

Fig. 2. FPGA internal signal flow chart of each module

Fig. 3. Schematic diagram of edge detection module

Fig. 4. Behavior level simulation waveform of edge detection module

Fig. 5. Schematic diagram of multi-channel delay processing module

Fig. 6. Behavior level simulation waveform of multichannel delay processing module

Fig. 7. Clock module schematic diagram

Fig. 8. Behavior level simulation waveform of clock module

Fig. 9. Input/output circuit design

Fig. 10. Experimental platform of digital delay and pulse generator

Fig. 11. Digital delay and pulse generator test results

Fig. 12. Operation diagram of BEPC II linear accelerator’s BPM electronics and the delay generator

Fig. 13. Test waveforms of digital delay and pulse generator and beam signal