High Power Laser and Particle Beams, Volume. 32, Issue 7, 074001(2020)

Design and implementation of digital delay and pulse generator of BEPC II linear accelerator

Jing Yang1...2, Jianshe Cao1,2, Yaoyao Du1,2, Lin Wang1, Yufei Ma1,2, Xing’er Zhang1,2, Qiang Ye1, Huizhou Ma1, Shujun Wei1, Junhui Yue1, and Yanfeng Sui12,* |Show fewer author(s)
Author Affiliations
  • 1Institute of High Energy Physics, Chinese Academy of Sciences, Beijing 100049, China
  • 2University of Chinese Academy of Sciences, Beijing 100049, China
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    A digital delay and pulse generator with high precision delay control, short rise time and flexible parameter adjustment is designed to meet the needs of BPM electronics for external trigger signals in the process of upgrading the BEPC II linear accelerator. An FPGA is used as the main controller. This paper mainly introduces the design principle and simulation results of edge detection module and multi-channel delay processing module based on FPGA software platform, and describes the design of FPGA and drive circuit, and its application in linear accelerator. The test results show that the output pulse of the digital delay generator has an adjustable delay range of 4 ns~4 μs, a minimum step of 4 ns, an adjustable error of 0.125%, a rise time of 2 ns, and a delay jitter of 135.4 ps.

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    Jing Yang, Jianshe Cao, Yaoyao Du, Lin Wang, Yufei Ma, Xing’er Zhang, Qiang Ye, Huizhou Ma, Shujun Wei, Junhui Yue, Yanfeng Sui. Design and implementation of digital delay and pulse generator of BEPC II linear accelerator[J]. High Power Laser and Particle Beams, 2020, 32(7): 074001

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    Paper Information

    Category: Particle Beams and Accelerator Technology

    Received: Jan. 15, 2020

    Accepted: --

    Published Online: Jul. 10, 2020

    The Author Email: Sui Yanfeng (syf@ihep.ac.cn)

    DOI:10.11884/HPLPB202032.200018

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