Silicon-based large-scale phased arrays are extensively deployed in millimeter-wave (mm-Wave) wireless communication networks to overcome the high path loss with a low cost^[1−9]. With the enhanced effective isotropic radiated power (EIRP) and the improved array gain, the N-element phased-array transceivers (TRX) can compensate for the extra path loss of 10log₁₀N dB and, thus, cover long communication distances. Nevertheless, the large-scale phased array faces growing challenges with the rapid development of mm-Wave 5G systems.

To increase throughput, 5G new radio (NR) networks adopt the broadband high-order modulated signals with improved spectral efficiency [e.g., orthogonal frequency division multiplexing (OFDM) 64-/256-quadrature amplitude modulation (QAM) signals]. The maximum bandwidth of a single carrier component (CC) is 400 MHz in frequency range 2 (FR2) networks^[10]. With carrier aggregation (CA) techniques, the instantaneous bandwidth of the transmitted signal is up to 16 × 400 MHz. In these scenarios, the beam squint of the large-scale phased array at wide steering angles can be considerable.

At the center frequency f₀ of 26 GHz, Fig. 1(a) depicts the beam deviation across different pointed angles of a phased array. The normalized frequencies f/f₀ of 0.94−1.06 in Fig. 1(a) correspond to the maximum signal bandwidth of about 3 GHz. As shown in Fig. 1(a), the phased array with a broadband 5G NR FR2 signal will lead to a severe beam squint of up to ±5° at large angles. Fig. 1(b) depicts the −1-dB and −3-dB beamwidths of the N × N uniform rectangular array (URA), showing that the −1-dB and −3-dB beamwidths of a 256-URA are less than 4° and 6°, respectively. According to Fig. 1(a) and Fig. 1(b), in the 5G NR FR2 scenario, the beamwidth of a large-scale phased array is comparable with a beam squint at wide steering angles. It leads to significant degradation of TX effective isotropic radiated power (EIRP) and RX gain. Besides, the narrow beamwidth results in the poor single-beam coverage of the large-scale phased array, increasing the design complexity and the implementation cost of the beam control circuits. For these reasons, the advantages of the phased array disappear as the number of elements increases. This motivates the research efforts on high-power, low-cost phased-array transceiver ICs, which can boost the EIRP without increasing the array element. For instance, according to the Friis transmission equation, for a given array size and receiving power, a phased-array transceiver IC with 3-dB higher output power can increase the communication distance by about 1.4 times without decreasing the beamwidth.

In this work, a 24−30 GHz 8-element dual-polarized phased-array transceiver (TRX) front-end IC for 5G NR FR2 is proposed. Fabricated in 65-nm CMOS, three 3GPP bands (i.e., n257/n258/n261) are fully covered. A two-way combining class-AB PA is integrated to boost the output power. A matching network co-designed (MNCD) on-chip T/R switch is integrated at the antenna interface to support time division duplex (TDD) mode. Section 2 describes the design details of the power-combing PA. The low-noise amplifier (LNA) and MNCD switch is presented in Section 3. Section 4 presents the transceiver architecture and describes other critical phased-array building blocks, including ATT and VMPS. The measurement results and conclusions are presented in Sections 5 and 6, respectively.

The output power of PA can be improved by combining either voltage or current. Fig. 2 depicts the power-combining PA in a phased-array TRX. The n-way series-combining PA shown in Fig. 2(a) stacks output voltage of each sub-PA to improve output power. The output-matching network (OMN) of each sub-PA transforms the load impedance Z_L/n to the optimum load impedance Z_opt. Hence, the series-combining network reduces the impedance transform ratio of sub-PA OMN. The characteristic impedance of the interconnection transmission line (T-line) should satisfy:

1ZS0,n=un−1+un−1+⋯+u1in=n−1n⋅ZL.

Otherwise, the impedance mismatching will lead to additional insertion loss of the series-combining network. Different Z_S0,n between sub-PAs complicates the design of series-combining PA. The n-way parallel-combining PA shown in Fig. 2(b) combines the output current of each sub-PA to improve output power. The OMN of each sub-PA transforms the load impedance n∙Z_L to Z_opt. The parallel-combining network increases the impedance transform ratio of sub-PA OMN. Unlike the series-combining one, the interconnection T-lines in the parallel-combining network share the same characteristic impedance:

2ZC0,1=ZC0,2=⋯=ZC0,n=unin=n⋅ZL.

It eases the design of multi-way, power-combining PA.

In TX mode, these two combining networks present their own advantages: The series-combining network reduces the design complexity of sub-PA OMN; the parallel-combining one reduces the design complexity of interconnection T-lines.

In RX mode, power-combining PA introduces parallel impedances Z_off,S and Z_off,C at the antenna interface, leading to RX insertion loss [see RX leakage in Figs. 2(c) and 2(d)]. In series-combining PA, the impedance transform ratio of sub-PA OMN is Z_opt : Z_L/n. As a result, Z_off,S in Fig. 2(c) can be addressed as

3Zoff,S=n⋅ZA=n⋅Zoff⋅ZLnZopt=ZoffZLZopt.

Similarly, the impedance transform ratio of sub-PA OMN in parallel-combining PA is Z_opt : nZ_L. Hence, Z_off,C in Fig. 2(d) can be addressed as

4Zoff,C=1n⋅ZB=1n⋅Zoff⋅nZLZopt=ZoffZLZopt.

According to Eqs. (3) and (4), in the ideal situation, the series- and parallel-combining PA present the same off-mode output impedances in RX mode. However, the two main reasons addressed below lead to the difference between Z_off,S and Z_off,C.

(a) The parasitic capacitance of the transformer in each sub-PA OMN. As depicted in Figs. 2(c) and 2(d), the parasitic capacitances C_PS and C_PC exist in the series- and parallel-combining networks, leading to the magnitude degradation of Z_A and Z_B. The impedance transform ratio of sub-PA OMN in the parallel-combining network is n²-times higher than that of the series-combining one. Thus, the implementation of sub-PA OMN in parallel-combining network requires more coils in the transformer, resulting in larger parasitic capacitance (i.e., C_PC > C_PS). On the other hand, according to Eqs. (3) and (4), Z_B is n²-times higher than Z_A. For these reasons, the product of Z_B and C_PC is much higher than that of Z_A and C_PS. Consequently, the impedance magnitude of Z_B in parallel with C_PC is

5|ZB//C|=ZB1+(ωCPCZB)2→(ωCPCZB)2≫11ωCPC.

The large product of Z_B and C_PC make Z_B//C deviate from its ideal value Z_B, and further make Z_off,C deviate from its ideal value addressed in Eq. (4). In contrast, the impedance magnitude of Z_A in parallel with C_PS is

6|ZA//C|=ZA1+(ωCPSZA)2→(ωCPSZA)2≪1ZA.

The small product of Z_A and C_PS ensures that Z_A//C is close to its ideal value Z_A. As a result, Z_off,S is close to its ideal value addressed in Eq. (3).

(b) The interconnections between each sub-PA OMN. In the n-way parallel-combining network, sub-PA OMNs are combined by interconnection T-lines, the characteristic impedance of which is nZ_L [see Eq. (2)]. In RX mode, these interconnection T-lines combine n-way Z_B//C in parallel, yielding Z_off,C. According to Eq. (4), Z_B//C is addressed as

7ZB//C=nZLZoffZopt//1jωCPC=nZLZoffZopt+n⋅jωCPCZLZoff≠nZL.

Since Z_B//C is not equal to the characteristic impedance of nZ_L, the interconnection T-lines will induce impedance transformation. It makes Z_off,C deviate from its ideal value addressed in Eq. (4). In contrast, in the n-way series-combining network, Z_A//C is in series with each other. The magnitude degradation of impedance induced by interconnection T-line characteristic impedance mismatch is alleviated. Moreover, by optimizing the layout floorplan^[11], the length of the interconnection T-lines in the series-combining network can be reduced, ensuring that Z_off,S is close to its ideal value, as addressed in Eq. (3).

According to these two reasons addressed above, in RX mode, the off-mode impedance at the antenna interface of the n-way series-combining PA is higher than that of the n-way parallel-combining one (i.e., Z_off,S > Z_off,C), leading to the reduced RX leakage, and, thus, ensuring the lower RX insertion loss. In this work, the proposed PA is implemented with the two-way series-combining network, boosting the output power without inducing significant insertion loss in RX mode.

As depicted in Fig. 2(a), in series-combining PA, the length of interconnection T-lines is mainly decided by the distance between each sub-PA. The active core and supply network of each sub-PA consume chip area, becoming the bottleneck of reducing the length of interconnection T-lines.

To tackle this, the distributed-active transformer^{[12, 13]} (DAT) combining network is proposed. The schematic is depicted in Fig. 3. DAT moves sub-PA differential OMN from PA_n output to the differential terminal between PA_n and PA_n-1. Note that the sub-PAs share the same active core. The minus terminal of PA_n-1 is equivalent to that of PA_n. Hence, as a traditional series-combining network, DAT stacks output voltage of sub-PA to boost the output power. In contrast, as shown in Fig. 3, in DAT, the bottleneck of reducing the length of sub-PA OMN interconnection T-lines is the distance of the differential signal path, which is relatively small. As a result, DAT significantly reduces the length of interconnection T-lines. In this work, the two-way series-combining network is implemented as DAT.

Fig. 4 depicts the schematic of the proposed four-stage power-combining PA, including the two-stage common-source (CS) amplifier and the two-stage two-way cascode amplifier. The details of the T/R switch will be addressed in the next section.

Each CS transistor pairs in Fig. 4 utilizes the differential capacitive neutralization techniques to improve gain and stability. Inductors 210-pH L₂ and 150-pH L₃ are introduced at the cascode intermediate nodes of two cascode stages, reducing the amplitude-to-phase (AM–PM) distortions from above 9° to around 3° without degrading PA output power and efficiency^[1]. To further reduce the AM-PM distortion, C_g2, C₃ and L₄ are introduced at the output stage to enable wideband 2^nd harmonic filtering. The layouts of cascode active cores are developed based on Ref. [1], realizing wideband 2^nd harmonic filtering with compact size.

Fig. 5 depicts the schematic of the proposed output stage in common mode. Three 2^nd harmonic traps provide three signal paths for the 2^nd harmonic (i.e., Z_in1, Z_in2 and Z_in3). Z_in1 consists of C₄ and L₄. Z_in2 consists of L₃ and C₃. Z_in3 consists of neutralization capacitance C_n, transistor parasitic capacitance C_gd, inductance in the inter-stage transformer L_MN and C_g2. Note that the common mode capacitance C_cm of the transformer is small. Hence, it is omitted in the following discussion. Among these harmonic traps, C_g2, C₃, L₄ are blocked by the differential virtual ground at fundamental frequency. As a result, the PA design procedure is: First, complete the design of C₄, L₃, L_MN, C_n according to the performance at fundamental frequency; second, adjust the value of C_g2, C₃, L₄ to enable wideband 2^nd harmonic filtering. The resonant frequency of each harmonic trap is

8f0,Zin1=f(L4)=12π2L4C4,

9f0,Zin2=f(C3)=22πL3C3,

10f0,Zin3=f(Cg2)=12π4(Cn+Cgd)+2Cg2LMNCg2(Cn+Cgd).

In this work, the values of C₄, L₃, L_MN, C_n are 100 fF, 150 pH, 73.1 fF, and 228.2 pH, respectively. C_gd shares the same capacitance with C_n. Based on these parameters, L₄, C₃, C_g2 are respectively implemented with values of 43.4 pH, 135.1 fF, and 240.5 fF, resulting in the f_0,Zin1, f_0,Zin2, and f_0,Zin3 of 54, 50, and 58 GHz. Hence, three 2^nd harmonic traps fully cover the band of 2 × 24 GHz to 2 × 30 GHz, enabling the wideband 2^nd harmonic filtering. Fig. 6 depicts the simulated AM–PM of the proposed output stage across frequencies. With inductor L₃ and three-stage 2^nd harmonic trap, the proposed output stage demonstrates a simulated AM–PM of 0.8°−1.4° across the 3GPP n257/n258/n261 bands. Similar to the output stage, 2^nd harmonic traps are also integrated in driver stages to further mitigate the AM–PM.

Based on the proposed active cores, a two-way DAT is designed and integrated at the PA output. Fig. 7 depicts the schematic of the proposed DAT, which serves as both power combiner and OMN. It combines the output power of sub-PA while transforming 50-Ω load impedance to sub-PA Z_opt of 30 + j × 25 Ω. Hence, the area of power-combining PA is reduced, facilitating the PA integration in the phased-array TRX IC.

As shown in Fig. 7, the proposed DAT consists of two sub-transformers (sub-XFMRs), the impedance transformation ratio and characteristic impedance of which are 1 : 1 and 25 Ω, respectively. The equivalent inductance of interconnections L_inter and parallel capacitance C₄ further transform 25 Ω to Z_opt. However, the 90° turning of L_inter will lead to signal imbalance. To tackle this issue, the isolation resistances R_ISO of 12 Ω are introduced, as plotted in Fig. 7. It absorbs the imbalanced signal power, avoiding potential performance degradation. Similar to the isolation resistance in the Wilkinson combiner, R_ISO can also improve the isolation between two sub-PAs. With R_ISO, EM-simulation results show that the isolation is improved by at least 24 dB. Across 24−30 GHz, the EM-simulated isolation between two sub-PAs is from 31 to 52 dB. High isolation is beneficial for the stability of the power-combining PA.

Across 24−30 GHz, the EM-simulated insertion loss of the proposed DAT is 0.7−0.9 dB. The four-stage power-combining PA demonstrates a simulated power gain of 39.0−39.6 dB with a simulated OP1dB of 20.0−20.9 dBm.

Fig. 8(a) depicts the schematic of the proposed LNA and the matching network co-designed (MNCD) on-chip T/R switch. LNA is implemented as one single-ended cascode stage and two differential CS stages. At the input cascode stage, the 114-pH L_ser is introduced to boost gain^[14]. The 72-pH L_deg is introduced to enable inductive source degeneration to facilitate simultaneous noise and gain matchings. EM-simulation results show that the proposed LNA demonstrates a small signal gain of 28.1−28.7 dB and noise figure (NF) of 3.3−3.8 dB across 24−30 GHz.

The RF switch is implemented as the MNCD on-chip T/R switch. The switch transistor M_SWT is implemented with three-stacked resistive body-floating technique^[15] to sustain large voltage swing and reduce off-mode capacitance C_off. The schematic is depicted in Fig. 8(b). In TX mode, M_SWT is turned on, LNA is turned off. L_S and the T-line with an electrical length of βl together transform the turn-on resistance of M_SWT to high impedance^[1], reducing the insertion loss in TX mode. The inductance of L_S is 286.3 pH with a quality factor of above 17.6 across 24−30 GHz. In RX mode, PA and M_SWT are both turned off. The input-matching network of LNA consists of C_off, L_S, C_block and L_P. As depicted in Fig. 8, off-mode PA will induce RX leakage in RX mode, resulting in the additional RX insertion loss.

Fig. 9 depicts the simplified off-mode PA AC model in RX mode. The output impedance of off-mode PA is simplified as a parallel RC tank, which consists of 958-Ω R_off,PA and 110-fF C_off,PA. Sub-XFMRs in DAT are simplified as a T-section model^[16], including 110.3-pH L_S1, 167.8-pH L_P and 14-pH L_S2. L_S2 is omitted in the following discussion due to the low inductance. As shown in Fig. 9, R_off,PA, C_off,PA, C_t and L_S1 can be the equivalent to C_eq in series with R_eq. Proper C_t is able to introduce parallel resonance between C_eq and L_P, and, thus, reduce the RX leakage induced by off-mode PA. In RX mode, the switched capacitor C_t satisfies:

11Ct=1ω2(LP+LS1)−Coff,PA.

In this work, the capacitances of C_t in RX and TX modes are 14.9 and 50 fF, respectively. It introduces parallel resonance at 27 GHz in RX mode and enables 2^nd harmonic filtering and power matching in TX mode. The switch transistor in C_t is implemented with four-stacked resistive body-floating technique^[14] to sustain large voltage swing of PA.

Nevertheless, the limited R_off,PA and the parasitic resistance of L_S1 degrades the quality factor of the parallel resonance, and, thus, the off-mode PA still leads to additional RX leakage. To quantify the impact of the lump parameters addressed above on RX leakage, R_eq and C_eq can be addressed as:

12Req=Roff,PA1+QC2+ωLS1QLs1,

13Ceq=1+QC2ωRoff,PAQC−ω2LS1(1+QC2),

where Q_LS1 is the quality factor of L_S1, Q_C is the total quality factor of C_off,PA and C_t:

14QC=ωRoff,PA(Coff,PA+Ct)=Roff,PAω(LP+LS1).

Combining Eqs. (12)−(14), the quality factor of C_eq can be addressed as:

15Qeq=1ωReqCeq=(QCRoff,PA/ωLS1)−QLS1(1+QC2)(Roff,PA/ωLS1)+1+QC2.

Hence, the minimum RX leakage induced by off-mode PA is

16RXLeakage[dB]=10log10(2(1+Qeq2)2(1+Qeq2)+ωZLQeqCeq),

where Z_L is the load impedance at the antenna interface (i.e., 50 Ω). Eqs. (12)−(16) clearly show that the RX leakage correlates to R_off,PA, L_S1, and L_P. Among these parameters, R_off,PA is decided by the transistor size and output power of PA. L_P affects the coupling coefficient and insertion loss of PA OMN. Hence, R_off,PA and L_P have been determined during the PA design procedure. The RX leakage is up to L_S1 and its quality factor Q_LS1.

According to Eq. (16), Fig. 10 depicts the simulated RX leakage contours across different L_S1 and Q_LS1, clearly showing that small L_S1 with high Q_LS1 results in low RX leakage. As shown in Fig. 7, L_S1 consists of the equivalent series inductance of sub-XFMR and the interconnection L_inter. The former can be reduced by increasing the coupling coefficient of sub-XFMR. Hence, L_inter is the bottleneck of reducing L_S1.

In this work, L_inter is routed in 45° to reduce the electrical length. The spacing is set to 2 μm to reduce the characteristic impedance. Short electrical length and low characteristic impedance result in the low equivalent inductance L_inter of 51.1 pH. Besides, L_inter and the primary coil of sub-XFMR is implemented with the widest top thick metal to reduce the series parasitic resistance, and, thus, to improve Q_LS1. According to the EM-simulation results, in this work, the inductance of L_S1 is 110.3 pH with a Q_LS1 of 14.9. Based on this inductance, the off-mode PA introduces a parallel impedance with a peak magnitude of 457 Ω at the antenna interface, leading to a RX insertion loss of 0.45 dB at 27 GHz. With the 0.2-dB insertion loss induced by the “βl T-line” (see Fig. 8), the proposed MNCD switch leads to RX insertion loss of less than 0.7 dB at 27 GHz.

To evaluate the insertion loss of the proposed MNCD switch across frequencies, Figs. 11(a) and 11(b) respectively depict the EM-simulated critical performances of the proposed PA and LNA with or without the proposed MNCD switch. As shown in Fig. 11, across the 3GPP n257/n258/n261 bands, the proposed MNCD switch respectively presents the insertion losses of 0.5−0.7 dB and 0.6−1.0 dB in TX and RX modes, excluding the insertion losses of PA output and LNA input matching networks. With the proposed MNCD switch, the proposed PA demonstrates the simulated power gain of 38.5−39.1 dB with the OP1dB of 19.5−20.4 dBm, the proposed LNA presents the simulated gain of 27.5−27.8 dB with the NF of 3.9−4.7 dB.

Fig. 12 depicts the block diagram of the mm-Wave 5G 8-element dual-polarized phased-array TRX IC. The dual-polarized power distribution network is implemented as two individual differential Wilkinson combiners/splitters. Two baluns are integrated at the common interface to enable the single-ended RF signal I/O. In each element, the TX chain consists of a four-stage PA, an active PS, a two-stage driver amplifier (DA) and an ATT. The RX chain consists of a three-stage LNA, an active PS, a DA, an ATT, and a two-stage DA. In both TX and RX chains, ATT is integrated far away from the antenna interface to reduce the impact of gain tuning on TX linearity and RX NF. The proposed MNCD switch is integrated at the antenna interface to support TDD mode. Critical building blocks including the temperature sensor and serial peripheral interface (SPI) are integrated as well to support large-scale phased-array applications. The details of ATT and PS are addressed in the following.

In this work, gain control is achieved by a 6-bit differential switched ATT^[17], enabling the gain compensation and sidelobe suppression. Fig. 13 depicts the simplified schematic. The proposed ATT consists of seven switched ATT cells, including three Π-type cells for 8-dB step, two T-type cells for 2-/4-dB steps and two simplified T-type cells for 0.5-/1-dB steps. 16-dB step is achieved by cascading two 8-dB cells (i.e., bit5 in Fig. 13). The parallel transistors in ATT are implemented as stacked transistors to improve linearity.

Simulated in the TRX element, the ATT presents a gain range of 31.5 dB and a gain resolution of 0.5 dB in both TX and RX modes. Across 24−30 GHz, the simulated RMS gain errors are less than 0.14 and 0.24 dB in TX and RX modes, respectively.

In this work, the 6-bit VMPS is utilized to fully cover the 360° phase shifting range with high phase resolution and low additional gain error. Fig. 14 depicts the schematic of the VMPS. The transformer-based I/Q modulator at the input generates in-phase and quadrature (I/Q) signals^[18]. Across 24−30 GHz, the phase and magnitude errors are less than 0.5° and 0.3 dB, respectively. Next, the I/Q signals are differently weighted by the variable gain amplifier (VGA) and combined at the output to enable phase shifting. The schematic of VGA is depicted in Fig. 15. The VGA achieves gain control by combining differently weighted in-phase and phase-inverted signals. In either I or Q signal path, the VGA enables the phase-inverted gain tuning when N is 7 to 12. When N is 0 to 5, the in-phase gain tuning is performed. The proposed phase-inverting VGA ensures the 360° phase shifting range of VMPS. Finally, 64 phase states are selected to cover the 360° phase shifting range with high phase resolution of 5.625° and low additional gain error.

Simulated in the TRX element, the VMPS presents a phase shifting range of 360° and a phase resolution of 5.625° in both TX and RX modes. Across 24−30 GHz, the simulated RMS phase errors are less than 0.9° in both TX and RX modes. The DC power consumption is only 3.8 mW.

Fabricated in 65-nm bulk CMOS, the proposed dual-polarized TRX IC occupies a total area of 6.6 × 5.1 mm². The die micrograph is shown in Fig. 16. On a millimeter-wave probe station, the continuous-wave (CW) and 5G NR FR2 modulation measurements are both performed with a 1.8-V supply voltage for cascode stages in PA/LNA and a 1-V supply voltage for other RF building blocks. All the DC supplies are wire-bonded to a PCB. And the RF signals are accessed by GSG probes.

The small signal CW measurement results in TX mode, including S-parameters, phase shifting and gain tuning, are depicted in Fig. 17. As shown in Fig. 17(a), in TX mode, the proposed dual-polarized TRX demonstrates a peak measured gain of 25.5 dB at the frequency of 28.5 GHz with a −3-dB bandwidth across 22.8 to 29.7 GHz. Across the operating band, the return loss at the antenna interface is from 6.5 to 11.1 dB. The 6-bit phase shifting is measured at the maximum gain mode and depicted in Fig. 17(b). Across the 3GPP n257/n258/n261 bands, the proposed TRX covers 360° shifting range with a phase resolution of 5.625° and a measured RMS error of 0.8° to 2.4°. The 6-bit gain tuning is further measured and plotted in Fig. 17(c). A 31.5-dB gain range is achieved with a gain step of 0.5 dB and a measured RMS error of 0.21 to 0.34 dB. The measured coupling between adjacent TRX elements is less than −48.7 dB across 24−30 GHz.

The small signal CW measurements, including S-parameters, phase shifting and gain tuning, are further performed in RX mode. The measurement results are depicted in Fig. 18. In RX mode, the proposed dual-polarized TRX presents a peak measured gain of 21.3 dB at the frequency of 28.0 GHz with a −3-dB bandwidth across 21.6 to 29.8 GHz, as shown in Fig. 18(a). The measured NF is from 4.1 to 5.2 dB across the operating band. The measured return loss at the antenna interface is from 12.2 to 20.9 dB. As in TX mode, the 6-bit phase shifting is measured at the maximum gain mode and depicted in Fig. 18(b). Across the 3GPP n257/n258/n261 bands, in RX mode, the proposed TRX covers the 360° shifting range with a phase resolution of 5.625° and a measured RMS error of 0.6° to 2.5°. The 6-bit gain tuning is further measured and plotted in Fig. 18(c). A 31.5-dB gain control range is achieved with a gain step of 0.5 dB and a measured RMS error of 0.16 to 0.26 dB. In both TX and RX modes, the proposed TRX covers the 3GPP n257/n258/n261 bands with flat frequency response, high-resolution 6-bit 360° phase shifting and high-resolution 6-bit 31.5-dB gain tuning.

Large-signal measurements are further performed in TX mode, including CW and modulation measurements. As shown in Fig. 19(a), the proposed TRX delivers a measured TX OP1dB of 19.2 to 20.8 dBm and a measured P_sat of 20.3 to 21.2 dBm across the 3GPP n257/n258/n261 bands. As depicted in Fig. 19(b), the corresponding PAEs are 17.0% to 21.1% and 17.3% to 22.0%, respectively. The modulation measurements are performed with 400-MHz 5G NR FR2 OFDM 64- and 256-QAM signal. The peak-to-average power ratios (PAPRs) are 11.6 and 12.0 dB, respectively. Fig. 19(c) depicts the measured output power of the proposed TRX under the 64-QAM signal with 5% EVM (i.e., −26.0 dB) and the 256-QAM signal with 3% EVM (i.e., −30.5 dB). The proposed TRX covers the 3GPP n257/n258/n261 bands with the output power of 11.0 to 12.4 dBm in the 64-QAM signal and 9.0 to 10.7 dBm in the 256-QAM signal.

Fig. 20 depicts the measured constellations, EVM and spectrum with 400-MHz 5G NR FR2 OFDM signal in TX mode. With the 400-MHz bandwidth, the optimal measured EVMs of the proposed TRX are 2.16% for 64-QAM signal and 2.23% for 256-QAM signal.

In Table 1, critical metrics are summarized and compared with recently published state-of-the-art silicon-based mm-Wave 5G TRX ICs. This work successfully covers three 3GPP 5G NR FR2 bands, including n257/n258/n261 bands, with the highest OP1dB of 20.8 dBm and an excellent NF of 4.1 dB.

This article presents an 8-element dual-polarized phased-array TRX front-end IC for mm-Wave 5G NR. In the 5G NR FR2 TDD scenario, the impact of PA power enhancement technologies on RX insertion loss are discussed. A four-stage wideband high-power class-AB PA with DAT and three-stage 2^nd harmonic traps is proposed, ensuring the mitigated AM−PM distortions across wide carrier frequencies without degrading other TX critical performances. In addition, an MNCD T/R switch is proposed to support TDD mode with reduced insertion loss in both TX and RX modes. Fabricated in 65-nm bulk CMOS, the proposed TRX demonstrates the state-of-the-art TX OP1dB of 20.8 dBm and the RX NF of 4.1 dB among bulk CMOS TRX beamformers. With the 400-MHz 5G NR FR2 OFDM signals, the TRX delivers an output power of 11.0−12.4 dBm in 64-QAM with 5% EVM and an output power of 9.0−10.7 dBm in 256-QAM with 3% EVM, covering 3GPP 5G NR FR2 operating bands of n257, n258, n261.