Nano-Micro Letters, Volume. 16, Issue 1, 264(2024)

Performance Limits and Advancements in Single 2D Transition Metal Dichalcogenide Transistor

Jing Chen1...3, Ming-Yuan Sun1, Zhen-Hua Wang1, Zheng Zhang1, Kai Zhang1, Shuai Wang1, Yu Zhang1,5, Xiaoming Wu2, Tian-Ling Ren2,*, Hong Liu4, and Lin Han1,4,56,** |Show fewer author(s)
Author Affiliations
  • 1Institute of Marine Science and Technology, Shandong University, Qingdao, 266237 Shandong, People’s Republic of China
  • 2School of Integrated Circuits and Beijing National Research Center for Information Science and Technology (BNRist), Tsinghua University, Beijing 100084, People’s Republic of China
  • 3BNRist, Tsinghua University, Beijing 100084, People’s Republic of China
  • 4State Key Laboratory of Crystal Materials, Shandong University, Jinan, 250100 Shandong, People’s Republic of China
  • 5Shenzhen Research Institute of Shandong University, Shenzhen, 518057, People’s Republic of China
  • 6Shandong Engineering Research Center of Biomarker and Artificial Intelligence Application, Jinan, 250100, People’s Republic of China
  • show less
    References(355)

    [61] [61] M. Bohr, in The evolution of scaling from the homogeneous era to the heterogeneous era, 2011 International Electron Devices Meeting. Washington, DC, USA. IEEE, (2011), pp. 1.1.1–1.1.6.

    [83] [83] "Frontmatter". Michael Alder: Das Haus als Typ, edited by Ulrike Zophoniasson-Baierl, Berlin, Boston: Birkhäuser, 2006, pp. i–vii.

    [84] [84] M.S. Elrabaa, I.S. Abu-Khater, M.I. Elmasry. in Low-Power VLSI design. ed.by M.S. Elrabaa, I.S. Abu-Khater, M.I. Elmasry, (Springer US; Boston, MA, 1997), pp. 1–5.

    [85] [85] R.D. Schrimpf, D.M. Fleetwood, in Radiation effects and soft errors in integrated circuits and electronic devices, vol. 34, (World Scientific Publishing, 2004), p. 348 (2004)

    [89] [89] S. Barraud, B. Previtali, C. Vizioz, J.M. Hartmann, J. Sturm et al., in 7-levels-stacked nanosheet GAA transistors for high performance computing, 2020 IEEE Symposium on VLSI Technology. Honolulu, HI, USA. (IEEE, 2020), pp. 1–2.

    [104] [104] B. Doris, I. Meikei, T. Kanarsky, Z. Ying, R.A. Roy et al., in Extreme scaling with ultra-thin Si channel MOSFETs, Digest International Electron Devices Meeting, pp. 267–270 (2002).

    [107] [107] C. Auth, C. Allen, A. Blattner, D. Bergstrom, M. Brazier et al., in A 22nm high performance and low-power cmos technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density mim capacitors. 2012 Symposium on VLSI Technology (VLSIT), pp. 131–132. (2012)

    [108] [108] J.P. Colinge, in Silicon-on-Insulator Technology: Materials to VLSI (Kluwer Academic Publishers, 2004).

    [123] [123] Y. Taur, T.H. Ning, Fundamentals of Modern VLSI Devices. (Cambridge University Press, New York, NY).

    [153] [153] S. Datta, Quantum Transport: Atom to Transistor (Cambridge University Press, 2005), pp.285–311

    [210] [210] N. Abele, R. Fritschi, K. Boucart, F. Casset, P. Ancey et al., in Suspended-gate MOSFET: bringing new MEMS functionality into solid-state MOS transistor, IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest. December 5–5, 2005, Washington, DC, USA. IEEE, Apr. (2006), pp. 479–481.

    [226] [226] Q. Wang, P. Sang, X. Ma, F. Wang, W. Wei et al., in Cold source engineering towards Sub-60mV/dec p-Type Field-effect-transistors (pFETs): materials, structures, and doping optimizations. 2020 IEEE International Electron Devices Meeting (IEDM). San Francisco, CA, USA. (IEEE, 2020), pp. 22.4.1–22.4.4.

    [244] [244] in Frontmatter and index (2002), pp. i-xiv.

    [253] [253] E. Ungersboeck, V. Sverdlov, H. Kosina, S. Selberherr, in Strain engineering for CMOS devices. 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings. Shanghai, China. (IEEE, 2006), pp. 124–127.

    [343] [343] N. Yang, Y.C. Lin, C.-P. Chuu, S. Rahman, T. Wu et al., in Computational screening and multiscale simulation of barrier-free contacts for 2D semiconductor pFETs, 2022 International Electron Devices Meeting (IEDM). San Francisco, CA, USA. (IEEE, 2022)., pp. 28.1.1–28.1.4.

    [344] [344] Y.-Y. Chung, B.-J. Chou, C.-F. Hsu, W.-S. Yun, M.-Y. Li et al., in First demonstration of GAA monolayer-MoS2 nanosheet nFET with 410 μA/μm ID 1V VD at 40 nm gate length. 2022 International Electron Devices Meeting (IEDM). San Francisco, CA, USA. (IEEE, 2022)., pp. 34.5.1–34.5.4

    [345] [345] A.-S. Chou, Y.-T. Lin, Y.C. Lin, C.-H. Hsu, M.-Y. Li et al., in High-performance monolayer WSe2 p/n FETs via antimony-platinum modulated contact technology towards 2D CMOS electronics, 2022 International Electron Devices Meeting (IEDM). San Francisco, CA, USA. (IEEE, 2022)., pp. 7.2.1–7.2.4.

    [346] [346] T.-E. Lee, Su Y.-C., B.-J. Lin, Chen Y.-X., Yun W.-S. et al., Nearly ideal subthreshold swing in monolayer MoS2 top-gate nFETs with scaled EOT of 1 nm 2022 International Electron Devices Meeting (IEDM). December 3–7, 2022. San Francisco, CA, USA. (IEEE, 2022).

    [348] [348] T.Y.T. Hung, M.-Z. Li, W.S. Yun, S.A. Chou, S.-K. Su et al., in pMOSFET with CVD-grown 2D semiconductor channel enabled by ultra-thin and fab-compatible spacer doping. 2022 International Electron Devices Meeting (IEDM). San Francisco, CA, USA. (IEEE, 2022), pp. 7.3.1–7.3.4.

    [354] [354] D.M. Sathaiya, T.Y.T. Hung, E. Chen, W.-C. Wu, A. Wei et al., in Comprehensive physics based TCAD model for 2D MX2 channel transistors. 2022 International Electron Devices Meeting (IEDM). San Francisco, CA, USA. (IEEE, 2022), 28.4.1–28.4.4.

    [355] [355] C.J. Dorow, A. Penumatcha, A. Kitamura, C. Rogan, K.P. O’Brien et al., in Gate length scaling beyond Si: mono-layer 2D channel FETs robust to short channel effects, 2022 International Electron Devices Meeting (IEDM). San Francisco, CA, USA. (IEEE, 2022), pp. 7.5.1–7.5.4.

    Tools

    Get Citation

    Copy Citation Text

    Jing Chen, Ming-Yuan Sun, Zhen-Hua Wang, Zheng Zhang, Kai Zhang, Shuai Wang, Yu Zhang, Xiaoming Wu, Tian-Ling Ren, Hong Liu, Lin Han. Performance Limits and Advancements in Single 2D Transition Metal Dichalcogenide Transistor[J]. Nano-Micro Letters, 2024, 16(1): 264

    Download Citation

    EndNote(RIS)BibTexPlain Text
    Save article for my favorites
    Paper Information

    Category: Research Articles

    Received: Apr. 10, 2024

    Accepted: Jun. 13, 2024

    Published Online: Jan. 23, 2025

    The Author Email: Ren Tian-Ling (rentl@tsinghua.edu.cn), Han Lin (hanlin@sdu.edu.cn)

    DOI:10.1007/s40820-024-01461-x

    Topics