Microelectronics, Volume. 53, Issue 3, 402(2023)

Design of a High Voltage and Low Power Comparator Circuit

OU Hongqi... LIU Yukui, FU Xiaowei, HAUNG Lei, ZHU Yukai, YIN Wanjun and WANG Lu |Show fewer author(s)
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    References(8)

    [1] [1] LEE S M, SONG T, CHO C, et al. Enhanced input range dynamic comparator for pipeline analogue-to-digital converter [J]. Elec Lett, 2009, 45(14): 728-730.

    [2] [2] WANG A L, CHEN C X, SHI C J R. Design and analysis of an always-on input-biased pA-current sub-nW mV-threshold hysteretic comparator for near-zero energy sensing [J]. IEEE Trans Circ & Syst I: Regu Pap, 2017, 64(9): 2284-2294.

    [3] [3] SONG W C, CHOI H W. 20-Msamplel/s low-power CMOS ADC [J]. IEEE J Solid-State Circuits, 1995, 30(5): 514-521.

    [5] [5] RAJ A, DIVVELA S Y, SINGH G, et al. Trade-off characteristics of hysteresis comparator used in noisy systems [C] // IEEE Dev IC. Kalyani, India. 2019: 413-417.

    [6] [6] NANDA S, PANDA A S, MOGANTI G L K. A novel design of a high speed hysteresis-based comparator in 90-nm CMOS technology [C] // IEEE ICIP. Pune, India. 2015: 388-391.

    [7] [7] WANG Y, YAO M, GUO B, et al. A low-power high-speed dynamic comparator with a transconductance-enhanced latching stage [J]. IEEE Access, 2019: 93396-93403.

    [9] [9] YANG W R, WANG J D. Design and analysis of a high-speed comparator in a pipelined ADC [C] // IEEE High Density Packag Microsyst Integr. Shanghai, China. 2007:1-3.

    [10] [10] SOLIS C J, DUCOUDRAY G O. High resolution low power 06 μm CMOS 40 MHz dynamic latch comparator [C] // IEEE Int Midwest Symp Circ Syst. Seattle, WA, USA. 2010: 1045-1048.

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    OU Hongqi, LIU Yukui, FU Xiaowei, HAUNG Lei, ZHU Yukai, YIN Wanjun, WANG Lu. Design of a High Voltage and Low Power Comparator Circuit[J]. Microelectronics, 2023, 53(3): 402

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    Paper Information

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    Received: Aug. 19, 2022

    Accepted: --

    Published Online: Jan. 3, 2024

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.220300

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