Optical Communication Technology, Volume. 47, Issue 6, 32(2023)
New 25 Gb/s CTLE circuit based on 40 nm CMOS process
[1] [1] SUN L, PAN Q, WANG K C, et al. A 26-28-Gb/s full-rate clock and data recovery circuit with embedded equalizer in 65-nm CMOS[J]. IEEE Transactions on Circuits and Systems, 2014, 61(7): 2139-2149.
[2] [2] AGRAWAL A, BULZACCHELLI J F, DICKSON T O, et al. A 19-Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45-nm SOI CMOS[J]. IEEE Journal of Solid-State Circuits, 2012, 47(12): 3220-3231.
[3] [3] KIM M, BAE J, HA U, et al. A 24-mW 28-Gb/s wireline receiver with low-frequency equalizing CTLE and 2-tap speculative DFE[C]//2015 IEEE International Symposium on Circuits and Systems, May 24-27, 2015, Lisbon, Portugal. Piscataway: IEEE, 2015: 1610-1613.
[5] [5] LEE J, LEE K, KIM H, et al. A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s video interface receiver with jointly adaptive CTLE and DFE using biased data-level reference[J]. IEEE Journal of Solid-State Circuits, 2020, 55(8): 2186-2195.
[6] [6] WANG H, LEE J. A 21-Gb/s 87-mW transceiver with FFE/DFE/analog equalizer in 65-nm CMOS technology[J]. IEEE Journal of Solid-State Circuits, 2010, 45(4): 909-920.
[7] [7] ZHANG K. A 4-Gb/s adaptive CTLE based on data edge counting and 8B10B coding for display port[C]//2022 7th International Conference on Integrated Circuits and Microsystems, October 28-31, Xi'an, China. Piscataway: IEEE, 2022: 453-458.
[8] [8] ATHARAV A, RAZAVI B. A 56-Gb/s 50-mW NRZ receiver in 28-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2022, 57(1): 54-67.
[9] [9] LEE J, WU K C. A 20-Gb/s full-rate linear clock and data recovery circuit with automatic frequency acquisition[J]. IEEE Journal of Solid-State Circuits, 2009, 44(12): 3590-3602.
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LI Bokai, HE Jin. New 25 Gb/s CTLE circuit based on 40 nm CMOS process[J]. Optical Communication Technology, 2023, 47(6): 32
Received: May. 19, 2023
Accepted: --
Published Online: Feb. 2, 2024
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