[1] [1] DEDARA O, BOJJA S, GUPTA N, et al. A 1.8 mW 450~900 MHz ±15 ps period jitter programmable multi-output clock generator with high supply noise tolerance in 28-nm CMOS process ［C］ // IEEE Nordic Circ Syst Conf (NORCHIP) & Int Symp Syst-on-Chip (SoC). Linkoping, Sweden. 2017: 1-4.

[2] [2] YANG X F, CHAN C H, ZHU Y, et al. A -246 dB jitter-FoM 2.4 GHz calibration-free ring oscillator PLL achieving 9% jitter variation over PVT ［C］ // IEEE Int Sol Sta Circ Conf (ISSCC). San Francisco, CA, USA. 2019: 260-261.

[5] [5] MANEATIS J G. Low-jitter process-independent DLL and PLL based on self-biased techniques ［J］. IEEE J Sol Sta Circ, 1996, 31(11): 1723-1732.

[6] [6] WEI X, LI P. The self-biased based PLL with fast lock circuit ［C］ // IEEE Int Conf Commun. Chengdu, China. 2010: 901-904.

[7] [7] SHEN K Y J, FAROOQ S F S, FAN Y P, et al. A 0.17-to-3.5 mW 0.15-to-5 GHz SoC PLL with 15 dB built-in supply noise rejection and self-bandwidth control in 14 nm CMOS ［C］ // IEEE Int Sol Sta Circ Conf (ISSCC). San Francisco, CA, USA. 2016: 330-331.

[8] [8] MANEATIS J G, KIM J, MCCLATCHIE I, et al. Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL ［J］. IEEE J Sol Sta Circ, 2003, 38(11): 1795-1803.