Fig. 1. Schematic diagram of ultrafast four-frame CMOS circuits

Fig. 2. Schematic diagram of 5T pixel unit circuit

Fig. 3. Schematic diagram of two sets of delay and control circuitry

Fig. 4. Schematic diagram of voltage controlled delayer

Fig. 5. Relationship between control voltage V_ctrl and relative delay

Fig. 6. Schematic diagram of the 4 delay lines

Fig. 7. Schematic circuity of row and column selector

Fig. 8. Relationship between output voltage of pixel and analog current

Fig. 9. Curve of voltage output signal of 8×8×4 pixel matrix

Fig. 10. Curve of exposure time resolution of the four-frame unit