Fig. 1. Block diagram of injection locking method

Fig. 2. The tunable high repetition rate narrow pulse laser. (a) Hardware scheme block diagram; (b) Physical diagram

Fig. 3. Schematic diagram of pulse current drive circuit

Fig. 4. Schematic of the chip implementing the select and fan-out functions

Fig. 5. Timing diagram of analog processing and driving circuit part

Fig. 6. Schematic diagram of bias current drive part

Fig. 7. Block diagram of the temperature control

Fig. 8. Relationship between laser temperature and the set voltage of DAC

Fig. 9. Temperature error acquisition, amplification and analog PID controller processing

Fig. 10. Schematic diagram of the voltage controlled constant current source circuit

Fig. 11. Power distribution of each part

Fig. 12. Output pulse laser waveform when internally triggered. (a) Time axis division 500 ps; (b) Time axis division 50 ps

Fig. 13. Output pulse laser waveform when externally triggered. (a) Time axis division 500 ps, including external trigger signal and output optical pulse; (b) Time axis division 100 ps

Fig. 14. Counts of pulse laser measured with single-photon detector

Fig. 15. Spectra of pulse laser before and after injection locking. (a) Before injection locking; (b) After injection locking

Fig. 16. Variation curve of pulse laser wavelength with time