Microelectronics, Volume. 53, Issue 2, 197(2023)

A 6 GHz Low Power PLL with -62.3 dBc Reference Spur

WEI Xueming1... WANG Fengmei1, XIE Leitong1, LIANG Dongmei1, YIN Renchuan1, XU Xinyu1 and XU Zhe2 |Show fewer author(s)
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  • 1[in Chinese]
  • 2[in Chinese]
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    References(12)

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    [2] [2] GAO X, KLUMPERINK E A M, GERAEDTS P F J, et al. Jitter analysis and a benchmarking figure-of-merit for phase-locked loops [J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2009, 56(2): 117-121.

    [3] [3] GAO X. Low jitter and low power PLL: towards the utopia [C] // International SOC Design Conference (ISOCC). Jeju, South Korea. 2019: 38-39.

    [4] [4] SHAO H B, LIN K, WANG B, et al. A high-performance charge pump with improved static and dynamic matching characteristic [C] // IEEE 11th International Conference on ASIC (ASICON). Chengdu, China. 2015: 1-4.

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    [7] [7] HE Y J, WANG Z Q, LIU H, et al. An 8.5-12.5 GHz wideband LC PLL with dual VCO cores for multi-protocol serdes [C] // IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS). Boston, MA, USA. 2017: 791-794.

    [8] [8] KIM K S, KIM K M, YOO C S. A fref/5 bandwidth type-II charge-pump phase-locked loop with dual-edge phase comparison and sampling loop filter [J]. IEEE Microwave and Wireless Components Letters, 2018, 28(9): 825-827.

    [9] [9] HERZEL F, FISCHER G, GUSTAT H, et al. An integrated CMOS PLL for low-jitter applications [J]. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2002, 49(6):427-429.

    [10] [10] DENG P Y, KIANG J F. A 5-GHz CMOS frequency synthesizer with an injection-locked frequency divider and differential switched capacitors [J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2008, 56(2): 320-326.

    [11] [11] LIN T H, KAISER W J. A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop [J]. IEEE Journal of Solid-State Circuits, 2001, 36(3): 424-431.

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    [14] [14] KHYALIA S K, NG Y S, WANG H, et al. A wide tuning range phase locked loop for 38 GHz transceiver in 65 nm CMOS [C] // IEEE International Symposium on Radio-Frequency Integration Technology (RFIT). Hualien, China. 2021: 1-3.

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    WEI Xueming, WANG Fengmei, XIE Leitong, LIANG Dongmei, YIN Renchuan, XU Xinyu, XU Zhe. A 6 GHz Low Power PLL with -62.3 dBc Reference Spur[J]. Microelectronics, 2023, 53(2): 197

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    Paper Information

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    Received: Mar. 4, 2022

    Accepted: --

    Published Online: Dec. 15, 2023

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.220080

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