Implementation of FPGA Based on High Throughput Parallel CRC-SCL Decoder of Polar Codes

Yanjun Liu; Yan Li; Yuyang Liu; Xiaoshuo Jia; Honghang Zhou; Xiaobin Hong; Jifang Qiu; Hongxiang Guo; Yong Zuo; Wei Li; Jian Wu

doi:10.3788/AOS202141.1706002

Acta Optica Sinica, Volume. 41, Issue 17, 1706002(2021)

Implementation of FPGA Based on High Throughput Parallel CRC-SCL Decoder of Polar Codes

Yanjun Liu^1,2、***, Yan Li^1,2、*, Yuyang Liu^1,2, Xiaoshuo Jia^1,2, Honghang Zhou^1,2, Xiaobin Hong^1,2, Jifang Qiu^1,2, Hongxiang Guo^1,2, Yong Zuo^1,2, Wei Li^1,2, and Jian Wu^1,2、**

Author Affiliations

¹School of Electronic Engineering, Beijing University of Posts and Telecommunications, Beijing 100876, China

²State Key Laboratory of Information Photonics and Optical Communications, Beijing University of Posts and Telecommunications, Beijing 100876, China

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Figures & Tables(8)

Fig. 1. Block diagrams of CRC-SCL. (a) Overview of CRC-SCL framework; (b) decoding butterfly graph of polar codes for N=4

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Fig. 2. Decoding flow chart of N=4 polar codes based on fully-unrolled pipeline architecture

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Fig. 3. Experimental setup for Polar-QPSK system

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Fig. 4. Results of back to back (B2B) experiments in polar-QPSK system. (a) Relationship between BER and ROP of CRC-SCL; (b) performance comparison of SC and CRC-SCL when R=1/2; (c) performance comparison of SC and CRC-SCL when R=4/5; (d) performance comparison of SC and CRC-SCL when R=2/3

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Fig. 5. Effect of quantization on error-correction performance of CRC-SCL decoder with N=256

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Fig. 6. Simulation results for CRC-SCL decoder with N=256 over AWGN channel

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Table 1. Effect of quantization on hardware resource of CRC-SCL decoder with N=256

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Table 1. Effect of quantization on hardware resource of CRC-SCL decoder with N=256

Bit number of LLR	Bit number of PM	LUTs	Regs	BRAM /bit	f /MHz	Throughput /(Gbit·s^-1)
13	15	435390(25%)	628883(18%)	648(24%)	156.25	40
12	12	417975(24%)	606723(18%)	631(23%)	156.25	40
8	12	332720(19%)	562752(15%)	451(17%)	156.25	40
6	12	292256(17%)	537807(15%)	402(15%)	156.25	40

Table 2. Comparison of high throughput polar decoders

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Table 2. Comparison of high throughput polar decoders

Method	This work	Ref. [10]	Ref. [14]	Ref. [15]
Algorithm	CRC-SCL	CRC-SCL(L=2)	SC	Fast-SSC-List
Length & Rate	256&0.5	1024&0.5	1024&0.5	512&0.83
IC type	FPGA	ASIC (40 nm)	ASIC (28 nm)	ASIC (28 nm)
Frequency /MHz	156.25	430	621	468
Throughput /(Gbit·s^-1)	16.25	3.25	318.00	12.00
$\frac{E_{b}}{N_{0}}$ /(10^-3 dB)	2.8	2.3	2.8	4.3

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Yanjun Liu, Yan Li, Yuyang Liu, Xiaoshuo Jia, Honghang Zhou, Xiaobin Hong, Jifang Qiu, Hongxiang Guo, Yong Zuo, Wei Li, Jian Wu. Implementation of FPGA Based on High Throughput Parallel CRC-SCL Decoder of Polar Codes[J]. Acta Optica Sinica, 2021, 41(17): 1706002

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Paper Information

Category: Fiber Optics and Optical Communications

Received: Feb. 6, 2021

Accepted: Mar. 23, 2021

Published Online: Sep. 3, 2021

The Author Email: Liu Yanjun (yanjun_std@163.com), Li Yan (liyan1980@bupt.edu.cn), Wu Jian (jianwu@bupt.edu.cn)

DOI:10.3788/AOS202141.1706002

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