The use of epitaxial MTBs as a 1D gate in FETs offers a promising future for the field of electronics. The authors have opened up new avenues for research and development in nanoelectronics, potentially leading to more efficient, scalable, and high-performance electronic devices. With advancements in scaling, performance, and integration, MTBs have the potential to revolutionize various applications, from low-power logic circuits to high-frequency and flexible electronics. The reduced channel current at lower gate voltages achieved by using MTBs as gates contributes to the development of energy-efficient, low-power electronic devices. The methods developed for the growth of large-area single crystals using MTBs can be scaled up for mass production. This scalability is essential for the commercial viability of 2D materials used in FETs in integrated circuits. Epitaxial MTBs can be integrated with existing semiconductor technologies, making them a viable option for next-generation electronic devices. Looking forward, the development of innovative electronic circuits using metallic MTBs as contacts and interconnects may be further facilitated by achieving more precise textures, such as uniform size, exact location, and orientation sequence of each crystal facet grain. Additionally, there is a need for more applications of large-area single crystals in integrated circuits beyond just using MTB as a gate. Factors such as complementary FETs, better density and packaging, lower cost, and gate capacitance must be considered and improved from transistors to integrated circuits^[8]. Investigating other 2D materials that can form MTBs will expand the range of possible applications. Combining different materials may lead to the discovery of new properties and functionalities. Moreover, researching the environmental stability and long-term reliability of devices using MTBs will be essential for their commercial success. This includes studying the effects of temperature, humidity, and other factors on device performance. At last but not least, developing methods for integrating MTBs into more complex circuits and systems will be an important step. This includes ensuring compatibility with other components and addressing challenges related to interconnects and packaging.

Additionally, this research not only facilitates the growth of epitaxial MoS₂ monolayer bicrystals but also integrates them into transistors to minimize gate length. The study addresses the inherent limitations in current silicon-based complementary metal−oxide−semiconductor (CMOS) technologies, particularly the high parasitic capacitance faced by three-dimensional (3D) field-effect transistor (FET) like Fin field-effect transistors (FinFETs) and gate-all-around FETs. By leveraging the unique one-dimensional (1D) conductive properties of MTBs in MoS₂, the research aims to push the boundaries of transistor miniaturization and performance, offering a potential pathway to more efficient and scalable FETs. By leveraging the ultimate 1D feature (width ~0.4 nm and length extending to tens of microns), the epitaxial MTBs serve as a 1D gate to construct integrated two-dimensional FETs. The pivotal role of the 1D MTB gate is evidenced by its ability to scale the depletion channel length down to 3.9 nm, significantly reducing channel current at lower gate voltages. Consequently, both single and array FETs have shown promising performance for low-power logic applications. The 1D epitaxial MTB gates in this study propose a novel synthetic route for integrating two-dimensional FETs that are resistant to high gate capacitance, pushing the boundaries of ultimate scaling. The research showed that these FETs could be fabricated at larger scales using chemical vapor deposition, overcoming the scalability limitations seen in previous works utilizing mechanical exfoliation.

Previously, in 2016, Ali Javey's group demonstrated MoS₂ transistors with a 1-nanometer gate length using single-wall carbon nanotubes^[6]. These transistors faced scalability issues due to the mechanical exfoliation limitations of 2D materials. In 2022, He Tian and Tian-Ling Ren's group achieved a record small gate length of 0.34 nm in MoS₂ transistors using the edge of monolayer graphene. These transistors are scalable, thanks to the chemical vapor deposition of graphene and MoS₂^[7].

MTBs, owing to their unique structure, can alleviate parasitic capacitance, a common challenge in traditional 3D FETs like FinFETs and gate-all-around FETs. MTBs in MoS₂ exhibit true 1D metallic characteristics, providing robust ohmic conduction pathways at room temperature. MTBs are formed by the reflection mirroring of two adjoining MoS₂ crystals with an exact 60° rotation, ensuring a uniform and reproducible structure. The MTBs maintain their metallic properties consistently within the MoS₂ monolayer host lattice, providing stable electrical characteristics. The deterministic epitaxial growth technique for MTBs is scalable, allowing for the production of large-area, high-quality monolayers that can be integrated into advanced electronic device as shown in the Fig. 1. This reduction in parasitic capacitance enhances the overall efficiency and performance of the transistors. In the realm of extreme scaling of Si CMOS technology, current 3D FETs, including FinFETs and gate-all-around FETs, face significant issues with high parasitic capacitance^[5] . However, this study offers a method to mitigate parasitic capacitance.

In recent years, there has been a significant increase in research focused on the growth of large-area single crystals. Rajan et al.^[1] recently achieved the growth of large-area monolayers of transition-metal chalcogenides through assisted nucleation. The quality of molecular beam epitaxy (MBE)-grown two-dimensional (2D) materials can be greatly enhanced by using sacrificial species deposited simultaneously from an electron beam evaporator during the growth process. This technique notably boosts the nucleation rate of the target epitaxial layer, resulting in large, homogeneous monolayers with improved quasiparticle lifetimes and fostering the development of epitaxial van der Waals heterostructures. Additionally, micrometer-sized silver films have been formed at the air-water interface by directly depositing electrospray-generated silver ions onto an aqueous dispersion of reduced graphene oxide under ambient conditions^[2]. Another study detailed a dual-limit growth method for large-area monolayer transition metal dichalcogenides, offering a general strategy for producing large-area monolayer transition-metal dichalcogenides (TMDC) films suitable for integrated circuit applications^[3]. However, these studies primarily emphasize the growth of high-quality large-area single crystals and offer limited discussion on their application in integrated circuits. The work of Moon-Ho Jo’s group addresses this by demonstrating the growth of mirror twin boundaries (MTBs), where two adjoining crystals mirror each other with a precise 60° rotation^[4] (Nat Nanotechnol, 2024, https://doi.org/10.1038/s41565-024-01706-1). This results in two crystal facets occurring in a 50 : 50 population ratio, ensuring that the embedded grain boundaries within the MoS₂ monolayer lattice are always MTBs, while also highlighting their application.