Fig. 1. Silicon hybrid multiplexer/demultiplexer. (a) Schematic diagram; (b) structure parameters and material platform

Fig. 2. Architecture of DNN-based inverse-design platform for silicon hybrid multiplexer/demultiplexer

Fig. 3. Optimization process of DNN model. (a) Relationship between the minimum validation loss and the number of neurons for different hidden layers when the epoch is 30000 times; (b) relationship between the number of epochs and validation loss

Fig. 4. Training results of neural network for inverse design: relationship between loss value and epoch

Fig. 5. Propagating mode fields of inverse-designed silicon hybrid multiplexer/demultiplexer. (a) Inputting TM₀ mode at port I₁; (b) inputting TE₀ mode at port I₁; (c) inputting TE₀ mode at port I₂

Fig. 6. Rlationships between transmission and operating wavelength of silicon hybrid multiplexer/demultiplexer

Fig. 7. Relationships between transmission and operating wavelength of device for different fabrication tolerances. (a) Error is -5 nm; (b) error is +5 nm

Fig. 8. Pictures of experimentally fabricated silicon chip. (a) Referenced PDM-link and waveguide; (b) silicon hybrid multiplexer/demultiplexer and MDM-link; (c) MDM-link; (d) functional region; (e) enlarged image of functional region

Fig. 9. Normalized experimental results of silicon hybrid multiplexer for multiplexing/demultiplexing. (a) TM₀ mode; (b) TE₀ mode; (c) TE₁ mode

Fig. 10. Inverse-design results with different expected transmittances. (a) T_TE1=0.5; (b) T_TE1=0.7; (c) T_TE1=0.9