Microelectronics, Volume. 53, Issue 5, 758(2023)

A High Linearity Gate Voltage Bootstrap Switch for Pipeline ADC

WANG Wei1, SHUI Shaolin1, DAI Jiahong1, CHIO U-fat1, LIU Binzheng1, YUAN Jun1, MA Li1, WANG Yuxin2, and WANG Yan2
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
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    References(10)

    [1] [1] ZAHRAI S A, ZLOCHISTI M, LE DORTZ N, et al. A low-power high-speed hybrid ADC with merged sample-and-hold and DAC functions for efficient subranging time-interleaved operation [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017, 25(11): 3193-3206.

    [2] [2] MOON K J, OH D R, CHOI M, et al. A 28-nm CMOS 12-bit 250-MS/s voltage-current-time domain 3-stage pipelined ADC [J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2020, 67(12): 2843-2847.

    [3] [3] MOON K J, OH D R, CHOI M, et al. A 28-nm CMOS 12-bit 250-MS/s voltage-current-time domain 3-stage pipelined ADC [J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2020, 67(12): 2843-2847.

    [4] [4] WU J, CHEN C Y, LI T, et al. A 240-mW 2.1-GS/s 52-dB SNDR pipeline ADC using MDAC equalization [J]. IEEE Journal of Solid-State Circuits, 2013, 48(8): 1818-1828.

    [5] [5] CHU M, KIM B, LEE B G. A 10-bit 200-MS/s zero-crossing-based pipeline ADC in 0.13-μm CMOS technology [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014, 23(11): 2671-2675.

    [6] [6] DEVARAJAN S, SINGER L, KELLY D, et al. A 12-b 10-GS/s interleaved pipeline ADC in 28-nm CMOS technology [J]. IEEE Journal of Solid-State Circuits, 2017, 52(12): 3204-3218.

    [7] [7] RAMKAJ A T, STRACKX M, STEYAERT M S J, et al. A 1.25-GS/s 7-b SAR ADC with 36.4-dB SNDR at 5 GHz using switch-bootstrapping, USPC DAC and triple-tail comparator in 28-nm CMOS [J]. IEEE Journal of Solid-State Circuits, 2018, 53(7): 1889-1901.

    [9] [9] MOHAMMADI A, CHAHARDORI M. A low-power, bootstrapped sample and hold circuit with extended input ranged for analog-to-digital converters in CMOS 0.18 μm [C]// IEEE 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD). Prague, Czech Republic. 2018: 269-272.

    [10] [10] LIU Q, SHU W, CHANG J S. A 1-GS/s 11-bit SAR-assisted pipeline ADC with 59-dB SNDR in 65-nm CMOS [J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2018, 65(9): 1164-1168.

    [11] [11] YANG P, WANG X, WANG C, et al. A 14-bit 200-Ms/s SHA-less pipelined ADC with aperture error reduction [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020, 28(9): 2004-2013.

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    WANG Wei, SHUI Shaolin, DAI Jiahong, CHIO U-fat, LIU Binzheng, YUAN Jun, MA Li, WANG Yuxin, WANG Yan. A High Linearity Gate Voltage Bootstrap Switch for Pipeline ADC[J]. Microelectronics, 2023, 53(5): 758

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    Paper Information

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    Received: Dec. 29, 2022

    Accepted: --

    Published Online: Jan. 3, 2024

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.220525

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