Microelectronics, Volume. 53, Issue 3, 396(2023)

A Rail-to-Rail I/O Operational Amplifier

YANG Yonghui... ZHANG Jinlong, ZHANG Guangsheng, HUANG Dong and ZHU Kunfeng |Show fewer author(s)
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    References(6)

    [1] [1] HUANG W, GAO J, YE P, et al. General analysis of resolution enhancement on time-synchronized sampling and its multi-resolution solution in 20GSPS acquisition system [J]. IEEE Access, 2019, 7: 81321-81332.

    [2] [2] KULEJ T. 04-V bulk-driven operational amplifier with improved input stage [J]. Circuits Syst Signal Process, 2014, 34(4): 1167-1185.

    [3] [3] JAYACHANDRAN R, SUBRAMANIAM P C, DHANARAJ K J. A novel tunable gain CMOS buffer amplifier for large resistive loads [J]. Integration, 2021, 77: 1-12.

    [4] [4] SOLOMON J E. The monolithic op amp: a tutorial study [J]. IEEE Journal of Solid-State Circuits, 1974, 9(6): 314-32.

    [8] [8] TSAI CH, WANG J H, CHANG CT, et al. High-speed rail-to-rail output buffer amplifier with dynamic-bias circuit [J]. Electronics Letters, 2009, 45(24) : 1199-1200.

    [10] [10] CENTURELLI F, MONSURRP, SCOTTI G, et al. An improved reversed miller compensation technique for three-stage CMOS OTAs with double pole-zero cancellation and almost single-pole frequency response [J]. Int J Circuit Theor Appl, 2020, 48(11): 1990-2005.

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    YANG Yonghui, ZHANG Jinlong, ZHANG Guangsheng, HUANG Dong, ZHU Kunfeng. A Rail-to-Rail I/O Operational Amplifier[J]. Microelectronics, 2023, 53(3): 396

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    Paper Information

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    Received: Aug. 16, 2022

    Accepted: --

    Published Online: Jan. 3, 2024

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.220298

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