Fig. 1. Schematic diagram of (a) FPC-MISFET and (b) EJ-MISFET.

Fig. 2. Schematic diagram of fabrication steps for proposed structure.

Fig. 3. (a) The I_D–V_DS characteristic curves and (b) blocking characteristic cuves from simulation and experiment to validate effectiveness of models used in simulation.

Fig. 4. Channel electric field distribution of C-MISFET (without field plates), FPC-MISFET, and EJ-MISFET.

Fig. 5. Off-state breakdown voltage from simulation of C-MISFET (without field plate), FPC-MISFET, and EJ-MISFET.

Fig. 6. Lateral electron density distribution in 2DEG for FPC-MISFET and EJ-MISHFET.

Fig. 7. Output characteristics of FPC-MISFET and EJ-MISFET.

Fig. 8. Transfer characteristics of FPC-MISFET and EJ-MISFET.

Fig. 9. Plot of optimized V_BK and R_ONversusN_N+ with N_N+ ranging from 6× 10¹⁸ cm⁻³ to 2.4× 10¹⁹ cm⁻³ and L_GN taking optimized value.

Fig. 10. Plot of optimized V_BK and R_ONversusL_GN with L_GN ranging from 3 μm to 14 μm and N_N+ bing 1× 10¹⁹ cm⁻³.

Fig. 11. Plot of V_BK and R_ONversusW_N with W_N ranging from 1 μm to 1.8 μm.

Fig. 12. Plot of V_BK and R_ONversusH_N with H_N ranging from 36 nm to 71 nm and H_P being 31 nm.

Fig. 13. Plot of V_BK and R_ONversusH_P with H_P ranging from 23 nm to 37 nm and H_N being 41 nm.

Fig. 14. Plot of V_BK and R_ONversusN_P, N_P ranging from 1 × 10¹⁷ cm⁻³ to 1 × 10¹⁸ cm⁻³.