Fig. 1. Structure and work flow of integrated chip

Fig. 2. Simulation result of coupled grating

Fig. 3. Relationship of distance between bottom of ZMWs and center of waveguide core with optical energy density at bottom of ZMWs

Fig. 4. Fabrication process of chip （The left and right sides of each image show different angles of the chip cross section）

Fig. 5. Chip characterization results

Fig. 6. Experimental apparatus and results for characteristic verification of integrated chips