Fast rising time electromagnetic pulse (FREMP) is a kind of transient electromagnetic interference. With short rise time and a large amount of energy, it can instantly cause the failure and paralysis of the device or even the entire system. When the circuit system is in electromagnetic interference (EMI) environment, there may be a reliability problem. High-intensity electromagnetic radiation can easily enter the system through coupling of the front door or the back door^[1-4].

CMOS technology plays a dominant role in digital circuits. In addition, electrostatic discharge (ESD) protection circuits are widely used in the input and output ports of CMOS digital circuits^[5]. They are relatively independent of the buffer circuit and logic circuit of the device, the FREMP coupled into the device not only interacts with the CMOS circuit, but also may act on the ESD protection circuit. Therefore, it is of practical significance to discuss the effect of FREMP on semiconductors. W. L. Vault conducted an electromagnetic pulse experiment on NAND TTL gate, and found that the failure susceptibility of a device depended on the ionizing radiation, the electrical stress pulse, and the polarity of the pulse^[6]. Sun Yi et al. analyzed and discussed the damage effects and mechanisms of CMOS NAND gate under the injection of electromagnetic pulse^[7]. Diode-triggered silicon-controlled rectifier (DTSCR) has the characteristics of snapback I-V behavior, low parasitic capacitance, high ESD current handling capability and small size^[8-9], thus it is a robust ESD protection device and has become the main electrostatic discharge protection component used in nano-scale processes. For low power consumption and high speed circuit design requirements, STI-DTSCR has obviously low leakage current and can provide ESD protection^[10]. At present, the SPICE modeling is mainly used to analyze the influence of ESD on circuit performance and to optimize the device. M. D. Ker et al. proposed a novel Native-NMOS-triggered SCR to protect the ultra-thin gate oxide of the input stage from ESD stress^[11].

This paper builds a CMOS electrostatic discharge protection circuit which adopts DTSCR as ESD protection circuit model with multiple physical parameters. Since the constructed DTSCR has a holding voltage less than 1.1 V, it is more beneficial to protect the low voltage circuit. At the same time, the transient simulation is carried out to simulate the discharge path of PS and ND modes under positive and negative FREMP. And the damage prediction and reliability analysis of ESD protection circuit are discussed in the case of pulse injection.

In this paper, the ESD-protected CMOS circuit with two DTSCR devices and an inverter device (INV) is taken as the research object, the circuit model is shown in Fig.1(a). In the specific simulation process, the Sentaurus TCAD is used to simulate device model. The cross-sectional view of traditional DTSCR device is shown in Fig.1(b). From top to bottom, there is an active region of 80 nm, a well depth of 4 μm, and a P-type doped substrate of 10 μm. And the STI shallow trench isolation method is used^[12]. The whole device model is 44.8 μm long and 10 μm wide. The substrate, P-well and N-well are lightly doped, and the active region is heavily doped with a Gaussian distribution. In Fig.1(c), the inverter device model consists of NMOS in the P-type substrate and PMOS in the N-well. The distance between the gates in the NMOS and PMOS regions is 5 μm, the gate length is 0.35 μm, the device length is 14.35 μm, and the width is 4 μm. The source and drain regions are heavily doped by Gaussian distribution. In addition, the initial temperature of the two devices is set to 300 K, and the lattice temperature of the hot electrode at the bottom of the device is fixed at 300 K.

In the process of fast rising time electromagnetic pulse injection, the temperature of the device will rise for a period of time. To describe the electrothermal model of the two-dimensional device more accurately, the thermodynamic model is needed to simulate the transport of carriers in the process of TCAD simulation^[13]. In this paper, the electrothermal effect is taken into account, and the non-isothermal model is adopted. It is assumed that the carrier and the lattice are in a thermodynamic equilibrium state to improve the accuracy of the simulation calculation. In this thermodynamic model, Poisson equation, current density equation and heat conduction equation need to be solved. The Poisson equation can be expressed as

$ {\nabla ^2}\psi = - \dfrac{q}{\varepsilon }(p - n + N_{\text{D}}^ + - N_{\text{A}}^ - ) $ (1)

where ε is the capacitance, q is the basic charge, n and p represent the electron and hole density respectively, $N_{\text{D}}^ + $ and $N_{\text{A}}^ - $ represent the ionized donor and ionized acceptor concentration respectively. In addition, the temperature gradient of the semiconductor will also affect the movement of the carrier, thus it is necessary to consider the influence of the internal temperature gradient caused by the self-heating effect on the carrier transport^[14]. The modified current density equation of electrons and holes can be expressed as

$ {{\boldsymbol{J}}_{\text{n}}} = - nq{\mu _{\text{n}}}\left( {\nabla {\phi _{\text{n}}} + {P_{\text{n}}}\nabla T} \right) $ (2)

$ {{\boldsymbol{J}}_{\text{p}}} = - pq{\mu _{\text{p}}}\left( {\nabla {\phi _{\text{p}}} + {P_{\text{p}}}\nabla T} \right) $ (3)

where µ_n(µ_p) is the electron (hole) mobility, $ {\phi _{\text{n}}} $($ {\phi _{\text{p}}} $) is the quasi-Fermi potential of electron (hole), and P_n(P_p) is the absolute thermoelectric power of electron (hole). In the thermodynamic model, the temperature T is represented by an equation related to the lattice temperature.

$ \begin{split} c\dfrac{{\partial T}}{{\partial t}} - \nabla \kappa \cdot \nabla T = & - \nabla \cdot [({P_{\text{n}}}T + {\phi _{\text{n}}}){{\boldsymbol{J}}_{\text{n}}} + ({P_{\text{p}}}T + {\phi _{\text{p}}}){{\boldsymbol{J}}_{\text{p}}}] - \left( {{E_{\text{c}}} + \dfrac{3}{2}{k_{\text{B}}}T} \right)\nabla \cdot {{\boldsymbol{J}}_{\text{n}}} -\\ & \left( {{E_{\text{v}}} + \dfrac{3}{2}{k_{\text{B}}}T} \right)\nabla \cdot {{\boldsymbol{J}}_{\text{p}}} + qR({E_{\text{c}}} - {E_{\text{v}}} + 3{k_{\text{B}}}T) + \hbar \omega {G_{{\text{opt}}}} \end{split} $ (4)

where c represents the lattice heat capacity, κ is the thermal conductivity of the material, and k_B is the Boltzmann constant, E_c and E_v represent the conduction band and valence band energy levels respectively, $ {G_{{\text{opt}}}} $ is he generation rate of photocarriers.

Meanwhile, the carrier mobility in the device is affected by factors such as temperature. In this paper, the Masetti model is used to simulate the doping-related mobility^[15], and the relevant expression is as follows

$ \;{ \mu _{{\text{dop}}}} = {\mu _{\min 1}}\exp \left( { - \dfrac{{{P_{\text{c}}}}}{{{N_{\text{i}}}}}} \right) + \dfrac{{{\mu _{{\text{const}}}} - {\mu _{\min 2}}}}{{1 + {{\left( {\dfrac{{{N_{\text{i}}}}}{{{C_{\text{r}}}}}} \right)}^\alpha }}} - \dfrac{{{\mu _1}}}{{1 + {{\left( {\dfrac{{{C_{\text{s}}}}}{{{N_{\text{i}}}}}} \right)}^\beta }}} $ (5)

where µ_min1, µ_min2 and µ₁ represent the reference mobility, and P_c, C_r and C_s represent the reference doping concentration. The parameter N_i in the formula is equal to N_A0+N_D0, where N_A0 indicates the doping concentration of the acceptor and N_D0 indicates the doping concentration of the donor. μ_const is the constant mobility and is obtained through the following formula

$ \;{ \mu _{{\text{const}}}}{\text{ = }}{\mu _{\text{L}}}{\left( {{T \mathord{\left/ {\vphantom {T {{T_0}}}} \right. } {{T_0}}}} \right)^{ - \zeta }} $ (6)

where T represents the reference mobility with T₀=300 K. $ \;{ \mu _{\text{L}}} $ represents the mobility which is related to the parameter ζ.

Combined with the above physical model and equivalent circuit model, the ESD protection circuit is simulated from two aspects of electrical characteristics and thermal characteristics. By using TCAD, the correlation curves of DTSCR and CMOS inverter are obtained by adding bias to the electrode and conducting quasi-static simulation through scanning voltage. The I-V characteristic of diode-triggered silicon-controlled rectifier is shown in Fig.2. The trigger voltage of the DTSCR model is 3.3 V, which is about the conduction voltage of four series diodes, and the holding voltage is approximately 1.1 V.

To simulate the damage effect of FREMP on ESD protection circuit, the square pulse is selected as the pulse waveform^[16-17]. In Fig.1(a), a voltage source signal and a resistor R_ns are used to generate a negative square pulse. In this paper, the rise time and amplitude of the square pulse are set to 1 ns and 20 V respectively, and the pulse width of the signal is 14 ns. The pulse signal is injected into the input port “in”, and the response of the FREMP to the circuit model is analyzed by observing the changes of voltage and current in the circuit.

As shown in Fig.3(a), before the injection of negative polarity pulse, the interior of SCR1 (which is connected to the VCC and the input port “in”) is in a high-impedance state and the ESD protection circuit does not start, so that the input voltage V_in will increase sharply with the injection of FREMP. When the voltage difference between the two ends of SCR1 reaches its trigger voltage, a large number of holes will be generated in the P_well, which recombine with electrons in N_well to form the forward current. At the same time, electrons in p+ region will also move towards n+ region to form the reverse current. Under the combined effect of current, the resistance of SCR1 is rapidly reduced and a large current discharge path is formed. As shown in Fig.3(b), due to the injection of negative pulses, the input signal with negative voltage polarity to V_CC and the discharge path of the ND mode is turned on, making SCR1 the main current leakage branch. The current I_SCR1 flowing through SCR1 is approximately equal to the input current I_in. The I_SCR1 reaches stability at 3 ns, and the input voltage V_in also decreases from the peak value to stable value. Since I_SCR2 (SCR2 is located between the input port “in” and ground) is close to zero, so SCR1 plays a major role in the negative FREMP injection process. Due to the existence of the gate capacitance of the CMOS inverter^[18], I_INV will change with V_in. During the change of V_in, V_out is always at 1 V, indicating that the inverter and the ESD protection circuit module works stably.

To analyze the influence of FREMP injection on the device in the circuit, the positive and negative square pulse with an amplitude of 400 V are taken as an example to analyze the heating process inside the device under FREMP. In this paper, the internal peak temperature of the device reaches the melting point of the silicon material (1 688 K) as the thermal damage criterion of the device. If the FREMP power injected into the device is high enough, the device may be partially burned during the pulse signal, resulting in irreversible physical damage, which further affects the circuit structure and function^[19-20]. Fig.4 shows the temperature changes inside each device during the injection of negative and positive pulse signals.

As the negative FREMP signal is injected into the circuit, a large amount of discharge current will flow through the device SCR1, resulting in a large amount of Joule heat inside the device, and the peak temperature of SCR1 rises, which may cause damage to the device, while the peak temperature inside the CMOS inverter only fluctuates slightly when FREMP is injected. The mechanism of thermal damage caused by FREMP on the device is further studied by observing the temperature distribution inside the device under positive and negative pulses. In Fig.5(a), during the process of simulating the negative pulse signal, it is determined that SCR1 is prone to burn out, and it is observed that the negative polarity signal has a great influence on SCR1, and there is a high temperature area represented by red. The hot spot is located in the main SCR path composed of n+/ P_well / N_well / p+ in the device, and there is no obvious hot spot in SCR2 and CMOS inverter.

Fig.6 shows the total current density, electric field intensity and mobility distribution of SCR1 under negative pulse. In Fig.6(a) and (b), it can be seen that the maximum area of current density distribution is located on the main SCR path, and that of electric field intensity is located in the corner of the active area. These results show that the corner of the active area on the main SCR path is the weakest part due to the heat accumulation effect, which is consistent with the hot spot position in Fig.5(a). The increase of temperature will reduce the mobility of carriers. Fig.6(c) shows that the mobility of the region near hot spot is influenced obviously.

To study the influence of pulse voltage signal parameters on the internal temperature of the device, the pulse signals with different voltage amplitudes and different rising edges are injected into the input port. In the third section, it was found that SCR1 was easily burned during negative pulse injection, while SCR2 and CMOS inverters did not change significantly. Therefore, the influence of FREMP signal parameters on SCR1 was mainly studied. Fig.7(a) shows the relationship between the internal peak temperature of SCR1 and the pulse amplitude. The rising edge of injected FREMP is fixed at 1 ns. When V_ns=20 V, the temperature of SCR1 is always maintained near 300 K, and the device is not damaged. With the increase of V_ns to 400 V, the maximum temperature inside the device also failed to reach the melting point of the material during the pulse duration, and then the temperature of SCR1 decreased with the disappearance of the pulse, and it was determined that there was no damage. When the signal amplitude increases to 1 kV, the energy absorbed by the device increases in the same time, and the internal temperature continues to rise. Finally, the highest temperature of SCR1 reaches the melting point of the material, confirming its damage.

On the other hand, when the amplitude of the injected pulse is fixed at 500 V, the relationship between the peak temperature inside the device and the rising edge of the pulse is extracted, as shown in Fig.7(b). It is found that the peak temperature inside the device decreases with the increase of pulse rising edge under a certain amplitude. For a longer rising edge, the transient power injected is smaller, resulting in a smaller amount of Joule heat. The overall heating process is relatively slow. As a result, it takes longer time for the device to reach the peak temperature during the pulse injection.

To study the relationship between the damage time of the ESD protection circuit and the amplitude of the injected FREMP, the width of the pulse is set to the time when the SCR burns out. The square pulses of different voltage amplitudes with the rising edge of 1 ns are injected into the input port of the circuit, and the damage amplitude threshold E under different pulse widths is extracted, as shown in Fig.8.

The result in Fig.8 shows that the damage amplitude threshold decreases with the increase of the pulse width, and it means that FREMP with a wider pulse width is more likely to make device burned. However, the trend of change is non-linear. In the case where the pulse width exceeds 12 ns, simply increasing the pulse width cannot significantly reduce the damage amplitude threshold. Through fitting curve, the equation describing the trend of change is obtained as follows:

$ \mathit{E} \mathrm{=0.14} \mathit{\tau } ^{ \mathrm{-0.43}} $ (7)

The correlation coefficient R² of the fitted curve is 0.92. It is found that the curve conforms to the classic Wunsch-Bell relationship and has good fitting accuracy^[21].

A CMOS circuit with ESD protection is constructed in this paper, and the FREMP effect is investigated both electrically and thermally using a CMOS inverter as an entry point. By injecting pulse signals with positive and negative polarities into the ESD protection circuit and simulating based on TCAD, the port transient signals of the circuit model are extracted and the reasons for signals change are analyzed and summarized. The simulation results of the FREMP pulse injection show that the device SCR1 has the risk of high-temperature damage under a negative pulse. And the device SCR2 is extremely susceptible to high-temperature damage under the injection of a positive pulse signal. Meanwhile, it is found that the vicinity of the two electrodes in the main SCR pathway of the device is a potential damage region by analyzing the temperature distribution map inside the device after the end of pulse injection. In addition, the relationships between the peak temperature and the amplitude and the rising edge of the pulse signal are obtained, respectively. By injecting square pulses with different voltage amplitudes from 20 V to 1 kV and rising edges from 0.2 ns to 2 ns into the input port of the ESD protection circuit, it is concluded that the higher the pulse signal power, the higher the peak temperature under a certain rising edge of the pulse signal. It is also found that the peak temperature inside the device decreases with the increase of pulse rising edge under a certain power of the pulse signal.

These results indicate that there is a potential risk of damage to the ESD protection circuit module in CMOS circuits under the action of high-power FREMP. The simulation results and analyses in this paper fill the gap in the research on the microwave effect mechanism of ESD protection circuits, which can subsequently enhance the protection of the circuits under FREMP pulses, and provide valuable references for the subsequent improvement of the reliability of the ESD protection circuits and prediction of the damage localization of the circuits.