[1] [1] WANG L SH, LI Y. The Jitter and Wander in Optical Transmission Network［M］. Beijing: Press of Beijing University of Posts and Telecommunications, 2002.

[2] [2] GURUMOORTHY V,PALERMO S. Supply regulation techniques for phase-locked loops ［C］.Circuits and Systems Workshop(DCAS 2009), Dallas IEEE,2009: 1-4.

[3] [3] van der TANG J D, VAUCHER C S. Design and optimization of a low jitter clock-conversion PLL for SONET/SDH optical transmitters ［C］.Electronics, Circuits and Systems(ICECS 2001), Poland Zakopane, IEEE,2001: 31-34.

[4] [4] ZHANG J SH, ZHENG J Y, WAN X P. Phase-Locked Loop Technologies［M］. Xi’an: Press of Xidian University, 2003.(in Chinese)

[5] [5] KYOOHYUN L, PARK CH H, KIM D,et al.. A low-noise phase-locked loop design by loop bandwidth optimization［J］. IEEE Journal of Solid-State Circuits, 2000,35(6): 807-815.

[6] [6] KROUPA V F. Phase Lock Loops and Frequency Synthesis［M］. West Sussex England: John Wiley & Sons Ltd, 2003.

[7] [7] XIANG G, KLUMPERINK E A M, GERAEDTS P F J, et al.. Jitter analysis and a benchmarking figure-of-merit for phase-locked loops［J］. IEEE Transactions on Circuits and Systems II: Express Briefs, 2009,56(2): 117-121.

[8] [8] KHO J, LOH C I, WUI H M, et al.. Extended analysis of SSN effect on phase-locked loop (PLL) circuit ［C］.Electrical Design of Advanced Packaging & Systems Symposium(EDAPS 2009). Hong Kong, IEEE, 2009: 1- 4.

[9] [9] PEDRO R, JOSEP P, JOAN B, et al.. Decoupled double synchronous reference frame PLL for power converters control［J］. IEEE Trans. on Power Electronics, 2007,22(2): 584-592.

[10] [10] KAMATH A S, CHATTOPADHYAY B A. 13 MHz input, 480 MHz output Fractional Phase Lock Loop with 1 MHz bandwidth［C］.Circuits and Systems (ISCAS 2010), Paris IEEE,2010: 501-504.

[11] [11] ARAKALI A, GONDI S,HANUMOLU P K. Analysis and design techniques for supply-noise mitigation in phase-locked loops［J］. IEEE Journal of Circuits and Systems I, 2010, 57(11): 2880-2889.