Fig. 1. Structure diagram of image intensifier

Fig. 2. Demand diagram for cathode gating signal

Fig. 3. Equivalent circuit diagram of MOSFET

Fig. 4. Diagram of output-stage drive circuit

Fig. 5. Schematic diagram of time bias circuit unit of D flip-flop

Fig. 6. Simulation of time bias circuit unit of D flip-flop

Fig. 7. Simulation diagram of two-stage cascaded bias of D flip-flop time bias circuit

Fig. 8. Circuit diagram of dead time control unit

Fig. 9. Diagram of dead time sequential logic

Fig. 10. Diagram of minimum pulse width trimming circuit

Fig. 11. Diagram of sequential logic of minimum pulse width trimming

Fig. 12. Block diagram of drive logic

Fig. 13. Diagram of partial drive logic

Fig. 14. Accelerated conduction (primary drive) circuit

Fig. 15. Accelerated conduction drive signal

Fig. 16. Signal holding (primary drive) circuit

Fig. 17. Accelerated shutdown (primary drive) circuit

Fig. 18. Hardware design

Fig. 19. Test platform

Fig. 20. Diagram of rising edge before acceleration

Fig. 21. Diagram of rising edge after acceleration

Fig. 22. Diagram of minimum pulse width output

Fig. 23. Diagram of high repetition frequency test for gating circuit

Fig. 24. Diagram of waveform jitter test