Microelectronics, Volume. 52, Issue 5, 886(2022)

A High-Speed Asynchronous FIFO for 100 Gbit/s Ethernet PCS

ZHAN Yongzheng1...2, LI Tuo1,3, HU Qingsheng4, ZOU Xiaofeng1,2, and WANG Changhong13 |Show fewer author(s)
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    References(15)

    [1] [1] TOYODA H, ONO G, NISHIMURA S. 100 GbE PHY and MAC layer implementations [J]. IEEE Commun Mag, 2010, 48(3): S41-S47.

    [2] [2] MARTIN A J, NYSTROM M. Asynchronous techniques for system-on-chip design [J]. Proceed IEEE, 2006, 94(6): 1089-1120.

    [3] [3] RUAN W H, HU Q S. A 0.18 μm CMOS transmit physical coding sublayer IC for 100G Ethernet [J]. J Semicond,2016, 37(3): 035005-1 - 035005-7.

    [4] [4] LI H K, WANG Q C, YU S Y. Design of asynchronous FIFO based on Verilog HDL [J]. Elec Des Engineer, 2019, 29(19): 107-116.

    [5] [5] L F X, WANG J Y, ZHENG X Q, et al. A 40 Gb/s SerDes transceiver chip with controller and PHY in a 65 nm CMOS technology [J]. J Harbin Instit Technol, 2019, 26(3): 50-57.

    [6] [6] NANAYAKKARA A, THAYAPARAN S. Optimization of receiver FIFO for IEEE 802.3ba 40 GBASE PCS sub layer [C]// ICOIN. Kota Kinabalu, Malaysia. 2016: 151-154.

    [7] [7] DU W H, CHANG M H, YANG H Y, et al. An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions [C]// IEEE SoC Conf. Taipei, China. 2011: 19- 23.

    [8] [8] HSU W S, HUANG P T, WU S L, et al. 28 nm ultra-low power near-/sub-threshold first-in-first-out (FIFO) memory for multi-bio-signal sensing platforms [C]// Int Symp VLSI-DAT. Hsinchu, China. 2016: 1-4.

    [9] [9] YOKOYAMA Y, ISHII Y, OKUDA H, et al. A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same/different row access mode [C]// IEEE A-SSCC. Seoul, South Korea. 2017: 13-16.

    [10] [10] BULZACCHELLI J F. Equalization for electrical links: current design techniques and future directions [J]. IEEE Sol Sta Circ, 2015, 7(4): 23-31.

    [11] [11] NII K, TSUKAMOTO Y, YABUUCHI M, et al. Synchronous ultra-high-density 2RW dual-port 8T-SRAM with circumvention of simultaneous common-row-access [J]. IEEEJ Sol Sta Circ, 2009, 44 (3): 977-986.

    [12] [12] CALIMERA A, MACII A, MACII E, et al. Design techniques and architectures for low-leakage SRAMs [J]. IEEE Trans Circ & Syst, 2012, 59(9): 1992-2007.

    [13] [13] KIM T H, LIU J, KIM C H. A voltage scalable 0.26 V, 64 kb 8T SRAM with Vmin lowering techniques and deep sleep mode [C]// IEEE CICC. San Jose, CA, USA. 2008: 407-410.

    [14] [14] SHIBATA N, WATANABE M, ISHIHARA T. A SOI multi-VDD dual-port SRAM macro for serial access applications [J]. IEICE Trans Elec, 2017, E100.C(11): 1061-1068.

    [15] [15] DU W H, HUANG P T, CHANG M H, et al. A 2 kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs [C]// Int Symp VLSI-DAT. Hsinchu, China, 2012: 1-4.

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    ZHAN Yongzheng, LI Tuo, HU Qingsheng, ZOU Xiaofeng, WANG Changhong. A High-Speed Asynchronous FIFO for 100 Gbit/s Ethernet PCS[J]. Microelectronics, 2022, 52(5): 886

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    Paper Information

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    Received: Oct. 15, 2021

    Accepted: --

    Published Online: Jan. 18, 2023

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.210404

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