Fig. 1. The operating principle of CTIA. (a) Schematic of CTIA; (b) Schematic of cascode; (c) Time sequence and \begin{document}${V}_{{\rm{out}}\_{\rm{ctia}}}$\end{document}; (d) \begin{document}${V}_{{\rm{out}}\_{\rm{ctia}}}$\end{document} vs \begin{document}${I}_{{\rm{det}}}$\end{document}

Fig. 2. (a) The proposed AGROIC schematic; (b) Equivalent circuit after \begin{document}${M}_{{\rm{ag}}}$\end{document} is turned on

Fig. 3. (a) \begin{document}${V}_{{\rm{out}}\_{\rm{AG}}}$\end{document} vs time; (b)\begin{document}${V}_{{\rm{out}}\_{\rm{AG}}}$\end{document} vs \begin{document}${I}_{{\rm{det}}}$\end{document} at \begin{document}$ {t}_{s} $\end{document}

Fig. 4. (a) \begin{document}${V}_{{\rm{out}}\_{\rm{ctia}}}$\end{document}vs time; (b) \begin{document}${V}_{{\rm{out}}\_{\rm{ctia}}}$\end{document}vs \begin{document}${I}_{{\rm{det}}}$\end{document} when \begin{document}$ {T}_{i}=28\;\mathrm{\text{μs}} $\end{document}; (c) \begin{document}${V}_{{\rm{out}}\_{\rm{AG}}}$\end{document}vs time; (d) \begin{document}${V}_{{\rm{out}}\_{\rm{AG}}}$\end{document}vs \begin{document}${I}_{{\rm{det}}}$\end{document} when \begin{document}$ {T}_{i}=28\;\mathrm{\text{μs}} $\end{document}

Fig. 5. Schematic of three CDS circuits. (a) Fully-passive CDS; (b) Voltage buffer-based CDS; (c) Amplifier-based CDS^[11]

Fig. 6. The combined CTIA-CDS circuit. (a) Schematic; (b) Time sequence

Fig. 7. (a) Sample of \begin{document}${V}_{{\rm{out}}\_{\rm{ctia}}}$\end{document}; (b) The sample-hold voltage \begin{document}${V}_{{\rm{sh}}}$\end{document} vs \begin{document}${I}_{{\rm{det}}}$\end{document}

Fig. 8. (a) The schematic of anti-fold CDS; (b) Equivalent circuit after \begin{document}${M}_{{\rm{af}}}$\end{document} is turned on

Fig. 9. (a) \begin{document}${V}_{{\rm{sh}}\_{\rm{AF}}}$\end{document} vs time; (b) \begin{document}${V}_{{\rm{sh}}\_{\rm{AF}}}$\end{document} vs \begin{document}${I}_{{\rm{det}}}$\end{document}

Fig. 10. \begin{document}${V}_{{\rm{sh}}\_{\rm{AGAF}}}$\end{document} of combined AGROIC-AFCDS vs \begin{document}${I}_{{\rm{det}}}$\end{document}. (a) \begin{document}${V}_{{\rm{b}}\_{\rm{af}}} < {V}_{{\rm{b}}\_{\rm{ag}}}$\end{document}; (b) \begin{document}${V}_{{\rm{b}}\_{\rm{ag}}} < {V}_{{\rm{b}}\_{\rm{af}}}$\end{document}

Fig. 11. (a) \begin{document}${V}_{{\rm{sh}}}$\end{document}&\begin{document}${V}_{{\rm{cds}}}$\end{document}vs time; (b) \begin{document}${V}_{{\rm{sh}}}$\end{document}vs \begin{document}${I}_{{\rm{det}}}$\end{document} when \begin{document}$ {T}_{i}=28\;\mathrm{\text{μs}} $\end{document}; (c) \begin{document}${V}_{{\rm{sh}}\_{\rm{AGAF}}}$\end{document}&\begin{document}${V}_{{\rm{cds}}\_{\rm{AGAF}}}$\end{document}vs time; (d) \begin{document}${V}_{{\rm{sh}}\_{\rm{AGAF}}}$\end{document}vs \begin{document}${I}_{{\rm{det}}}$\end{document} when \begin{document}$ {T}_{i}=28\;\mathrm{\text{μs}} $\end{document}

Fig. 12. The analog signal path block diagram

Fig. 13. The block diagram of readout circuit

Fig. 14. Integration sample timing

Fig. 15. (a) The block diagram of testing system; (b) Photo of the testing platform

Fig. 16. (a) The schematic of testing circuit; (b) The timing sequence of testing

Fig. 17. The output noise acquisition. (a) The histogram of 100×100 segment when CDS-off; (b) The histogram of 100×100 segment when CDS-on

Fig. 18. The testing results of adaptive-gain function

Fig. 19. The testing results of anti-fold function