Optics and Precision Engineering, Volume. 22, Issue 11, 3114(2014)
Calibration of weight-error for pipelined ADCs
[3] [3] AMICO S D, COCCIOLO G, SPAGNOLO A, et al.. A 7.65-mW 5-bit 90-nm 1-Gs/s folded Interpolated ADC without calibration [J]. IEEE Transactions on Instrumentation and Measurement, 2014, 63(2):295-303.
[4] [4] FANG B N, WU J T. A 10-Bit 300-MS/s pipelined ADC with digital calibration and digital bias generation [J]. IEEE Journal of Solid-State Circuits, 2013, 48(3): 670-683.
[7] [7] XIONG ZH X, CAI M, HE X Y. Digital background calibration for A 14-bit 100-MS/s pipelined ADC using signal-dependent dithering [C]. Proceedings of IEEE International Conference of Electron Devices and Solid-State Circuits, Hong Kong, China, EDSSC, 2013: 1-2.
[8] [8] MATSUNO J, YAMAJI T, FURUTA M, et al.. All-digital background calibration technique for time-interleaved ADC using pseudo aliasing signal [J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2013, 60(5): 1113-1121.
[9] [9] KARANICOLAS A N, HAE-SEUNG L, BARCRANIA K L. A 15-b 1-Msample/s digitally self-calibrated pipeline ADC [J]. IEEE Journal of Solid-State Circuits, 1993, 28(12): 1207-1215.
[10] [10] DELIC-IBUKIC A, HUMMELS D M. Continuous digital calibration of pipeline A/D converters[J]. IEEE Transactions on Instrumentation and Measurement, 2006, 55(4):1175-1185.
[11] [11] GUSTAVSSON M, WIKNER J J, TAN N N. CMOS Data Converters for Communications[M]. Boston: Kluwer Academic Publishers, 2000.
[12] [12] YOUNG-JAE C, KYUNG-HOON L, HEE-CHEOL C, et al.. A Calibration-Free 14b 70MS/s 3.3 mm 2 235 mW 0.13 μm CMOS pipeline ADC with high-matching 3-D symmetric capacitors [C]. Custom Integrated Circuits Conference, San Jose, USA, 2006: 485-488.
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JIA Hua-yu, LIU Li, ZHANG Jian-guo. Calibration of weight-error for pipelined ADCs[J]. Optics and Precision Engineering, 2014, 22(11): 3114
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Received: Jun. 27, 2014
Accepted: --
Published Online: Dec. 8, 2014
The Author Email: Hua-yu JIA (jiahuayu@mail.xjtu.edu.cn)