To reduce and eliminate the interstage gain errors caused by capacitor mismatch and finite open-loop gain of an operating amplifier in a pipelined Analog to Digital Converter (ADC), a novel weight-based calibration technique on backend stages was presented. With proposed technique, a weight-based error model was built by merging error factors into a single term and the outputs of backend stages were utilized to calibrate the errors of front stages. To avoid interrupt normal conversion process, two extra stages were used in the calibration process to implement background calibration. During the normal conversion process and calibration process, the first seven stages of every signal path were all calibrated to increase the resolution and to eliminate errors. The improved technique was used in the implementation of 14 b, 80 MS/s pipelined ADC, and the ADC is with Chartered 0.18 μm, 1p6m CMOS process, a consume of 260 mW, and a chip area of 7.161 mm2. The test results show that the calibration technique improves dynamic and static performance and increases the precisions of pipelined ADCs.