[1] [1] KIM H, YOO C. A 6-Gb/s wireline receiver with intrapair skew compensation and three-tap decision-feedback equalizer in 28-nm CMOS ［J］. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020, 28(5): 1107-1117.

[3] [3] MASTAN S S K, SATYA P K, VENKATA R D. Adaptive decision feedback equalizer with dynamic principle for echo cancellation ［J］. Transactions of the Institute of Measurement and Control, 2018, 40(16): 4455-4471.

[4] [4] THAJ T, VITERBO E. Low complexity iterative rake decision feedback equalizer for zero-padded OTFS systems ［J］. IEEE Transactions on Vehicular Technology, 2020, 69(12): 15606-15622.

[5] [5] SANGEETHA R, VIDHYASHRI A, REENA M, et al. An overview of dynamic CMOS comparators ［C］// 2019 5th International Conference on Advanced Computing & Communication Systems (ICACCS). Coimbatore, India. 2019: 1001-1004.

[6] [6] CHEVELLA S, O’HARE D, O’CONNELL I. A low-power 1-V supply dynamic comparator ［J］. IEEE Solid-State Circuits Letters, 2020, 3: 154-157.

[9] [9] XU D, XU S, CHEN G. High-speed low-power and low-power supply voltage dynamic comparator ［J］. Electronics Letters, 2015, 51(23): 1914-1916.

[13] [13] WANG Y, YAO M, GUO B, et al. A low-power high-speed dynamic comparator with a transconductance-enhanced latching stage ［J］. IEEE Access, 2019, 7: 93396-93403.

[17] [17] MIYAHARA M, ASADA Y, PAIK D, et al. A low-noise self-calibrating dynamic comparator for high-speed ADCs ［C］// 2008 IEEE Asian Solid-State Circuits Conference. Fukuoka, Japan. 2008: 269-272.