In the SerDes circuits, the key of high speed data transmission is the equalized rate, so as the rate of data transmission increased, the rate of the decision feedback equalizer in the receiver of SerDes are also increasing. As a key component of adaptive decision feedback equalizer, delay time of the comparator determines the rate tolerance of the adaptive decision feedback equalizer. In order to meet requirement of low voltage for high speed comparator, this paper proposed a new comparator circuit which is suitable for high speed decision feedback equalizer. Based on a traditional two-tail comparator, this new comparator circuit was designed in TSMC 28 nm CMOS process. When the supply voltage is 1 V, the average delay time is 52.58 ps. It can meet the requirements of the decision feedback equalizer which data rate is up to 15 Gbit/s.