Chinese Journal of Quantum Electronics, Volume. 42, Issue 1, 111(2025)
FPGA implementation of high‐speed privacy amplification algorithm based on cellular automata
Fig. 3. FPGA modular design diagram for privacy amplification scheme
Fig. 4. FPGA sequence diagram of group reconciliation key processing
Fig. 5. FPGA sequence diagram of pipelined structure for group reconciliation key
Fig. 6. FPGA pipeline structure design diagram of privacy amplification scheme
Fig. 7. FPGA sequence diagram of pipelined structure for privacy amplification scheme
Fig. 8. Schematic diagram of privacy amplification improved scheme
Fig. 9. FPGA sequence diagram of improved pipeline structure for privacy amplification scheme
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Yekai LU, Enjian BAI, Xueqin JIANG, Yun WU, Genlong CHEN. FPGA implementation of high‐speed privacy amplification algorithm based on cellular automata[J]. Chinese Journal of Quantum Electronics, 2025, 42(1): 111
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Received: Mar. 27, 2023
Accepted: --
Published Online: Mar. 5, 2025
The Author Email: BAI Enjian (baiej@dhu.edu.cn)