Microelectronics, Volume. 53, Issue 4, 581(2023)

Design of a 25-28 Gbit/s CMOS High Sensitive Optical Receiver

JIN Gaozhe1... ZHANG Changchun1,2, YUAN Feng1, ZHANG Ying1 and ZHANG Yi1 |Show fewer author(s)
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
  • show less
    References(11)

    [1] [1] NAZARI M H, EMAMI-NEYESTANAK A. A 24-Gb/s double-sampling receiver for ultra-low-power optical communication [J]. IEEE J Sol Sta Circ, 2013, 48(2): 344-357.

    [2] [2] GEORGAS M. A monolithically-integrated optical receiver in standard 45-nm SOI [J]. IEEE J Sol Sta Circ, 2012, 47(7): 1693-1702.

    [3] [3] HUANG S H, CHEN W Z. A 25 Gb/s 113 pJ/b-108 dBm input sensitivity optical receiver in 40 nm CMOS [J]. IEEE J Sol Sta Circ, 2017, 52(3): 747-756.

    [4] [4] LEE Y S, HO W H, CHEN W Z. A 25-Gb/s, 21-pJ/bit, fully integrated optical receiver with a baud-rate clock and data recovery [J]. IEEE J Sol Sta Circ, 2019, 54(8): 2243-2254.

    [5] [5] RADI B, TAHERZADEH-SANI M, NEZAMI M S, et al. A 22-Gb/s time-interleaved low-power optical receiver with a two-bit integrating front end [J]. IEEE J Sol Sta Circ, 2020, 56(1): 310-323.

    [6] [6] PROESEL J E, TOPRAK-DENIZ Z, CEVRERO A, et al. A 32 Gb/s, 47 pJ/bit optical link with-117 dBm sensitivity in 14-nm FinFET CMOS [J]. IEEE J Sol Sta Circ, 2017, 53(4): 1214-1226.

    [7] [7] CEVRERO A, OZKAYA I, FRANCESE P A, et al. A 64 Gb/s 14 pJ/b NRZ optical-receiver data-path in 14 nm CMOS FinFET [C] // IEEE International Solid-State Circuits Conference. San Francisco, CA, USA. 2017: 482-483.

    [8] [8] LI H, SHARMA J, HSU C M, et al. A 100 Gb/s -83 dBm sensitivity PAM-4 optical receiver with integrated TIA, FFE and direct-feedback DFE in 28 nm CMOS [J]. IEEE J Sol Sta Circ, 2022, 57(1): 44-53.

    [10] [10] AHMED M G, TALEGAONKAR M, ELKHOLY A, et al. A 12 Gb/s -168 dBm OMA sensitivity 23 mW optical receiver in 65 nm CMOS [J]. IEEE J Sol Sta Circ, 2017, 53(2): 445-457.

    [13] [13] FU K L, LIU S I. A 64-Gb/s PAM-4 optical receiver with amplitude/phase correction and threshold voltage/data level calibration [J]. IEEE Transactions on Very Large Scale Integration Systems, 2020, 28(7): 1726-1735.

    Tools

    Get Citation

    Copy Citation Text

    JIN Gaozhe, ZHANG Changchun, YUAN Feng, ZHANG Ying, ZHANG Yi. Design of a 25-28 Gbit/s CMOS High Sensitive Optical Receiver[J]. Microelectronics, 2023, 53(4): 581

    Download Citation

    EndNote(RIS)BibTexPlain Text
    Save article for my favorites
    Paper Information

    Category:

    Received: Sep. 6, 2022

    Accepted: --

    Published Online: Jan. 3, 2024

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.220335

    Topics