Study On Optical Communications, Volume. 46, Issue 3, 23(2020)

Design and Implementation of Clock Recovery Algorithm for High Speed Optical Transmission System

XU Yuan-hao1、* and Lü Jian-xin2,3
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
  • 3[in Chinese]
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    References(3)

    [3] [3] Jeong C, Abullah A, Min Y, et al. All-Digital Duty-Cycle Corrector with a Wide Duty Correction Range for DRAM Applications[J].IEEE Transactions on Very Large Scale Integration(VLSI)Systems[J]. 2016,24(1):363-367.

    [9] [9] ITU-T G.709/Y.1331-2016. Interface for the Optical Transport Network[S].

    [12] [12] Liang J, Sheikholeslami A, Tamura H,et al.A 28 Gbit/s Digital CDR with Adaptive Loop Gain for Optimum Jitter Tolerance[C]//IEEE International Soild-State Circuits Conference.San Francisco,CA,USA:IEEE,2017:122-123.

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    XU Yuan-hao, Lü Jian-xin. Design and Implementation of Clock Recovery Algorithm for High Speed Optical Transmission System[J]. Study On Optical Communications, 2020, 46(3): 23

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    Paper Information

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    Received: Oct. 14, 2019

    Accepted: --

    Published Online: Jan. 19, 2021

    The Author Email: Yuan-hao XU (lessbean_94@sina.cn)

    DOI:10.13756/j.gtxyj.2020.03.005

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