Optics and Precision Engineering, Volume. 30, Issue 15, 1868(2022)
Visible light video denoising and FPGA hardware implementation
It is difficult to suppress the noise in static state of the existing filtering algorithm. Moreover, motion compensated filtering algorithm fails to effectively suppress noise. To solve these problems, a video denoising algorithm based on spatio-temporal filtering is proposed and implemented on the field programmable gate array (FPGA). The algorithm mainly uses Gaussian difference filtering to extract image features, and then applies spatial filtering to suppress high-frequency noise. Simultaneously, different denoising strategies are adopted for the segmented image area by feedback. Implementing hardware requires high-level synthesis tools to simplify programming, and is to make DDR3 control module to operate input and output of video stream between modules. Simulation results show that the proposed algorithm can be used for denoising. For different scenes, the peak signal-to-noise ratio can be increased by up to 15 dB in comparison with the denoising algorithm based on a non-subsampled contourlet (NSCT). After transplanting the algorithm to FPGA, the difference between PSNR and MATLAB simulation program was approximately 0.3 dB, and the running time was shortened by over 71.5%. Considering the real-time performance, PSNR achieves a better visible video denoising effect.
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Sixian ZHAO, Minjie WAN, Weixian QIAN, Lin ZHOU, Ajun SHAO, Qian CHEN, Guohua GU. Visible light video denoising and FPGA hardware implementation[J]. Optics and Precision Engineering, 2022, 30(15): 1868
Category: Information Sciences
Received: Mar. 25, 2022
Accepted: --
Published Online: Sep. 7, 2022
The Author Email: WAN Minjie (minjiewan1992@njust.edu.cn), GU Guohua (gghnjust@mail.njust.edu.cn)