Under the influence of Moore's law, the linewidth size of semiconductor manufacturing gradually reaches its limit. In the current process of 28 nm and below, the polycrystalline silicon gate etching is generally adopted by double-layer linked hard mask etching and polycrystalline silicon etching, which achieve effective control of key dimensions and increase the incidence of particle defects. In this paper, the source and formation mechanism of stick particle defects in the process of hard mask etching of polysilicon are analyzed. The removal of particles in the etching cavity and the electrostatic adsorption of the crystal backside are enhanced by precisely adjusting the release time of electrostatic-chuck (ESC) on the wafer and the release time of its own charge after the etching. The results show that when the release time of the wafer is increased by 2 s and the release time of the ESC charge is increased by 6 s, the stick particle defects can be reduced by about 80%. By controlling the associated process parameters to reduce defects, the use of expendable parts and the production costs can be effectively reduced.参考文献原文>Meng X G, Lu L, Chen F H, et al. Challenges and Solutions of 28nm Poly Etching \[C\]. Shanghai: Semiconductor Technology International Conference, 2017.