Space division multiplexing (SDM) technology has emerged to break through the transportation capacity limitations. As an important technical route to achieve SDM, mode division multiplexing (MDM) technology features high information density, low transmission cost, and low energy consumption. According to our investigation and research findings, there are many in-depth studies and reports on the implementation of various components in MDM systems. However, there is little research on the mode splitter. In MDM systems, mode-sensitive components have selectivity for input and output waveguide modes, and mode splitting based on a traditional mode demultiplexer is difficult to meet the requirements. Therefore, employing a mode splitter that does not change the mode order is an important method to improve the flexibility of MDM systems. The silicon-based mode splitter is a key device for constructing an on-chip MDM system to realize flexible routing of different modes. We propose a compact silicon-based mode splitter based on an adjoint optimization design algorithm and adopt the 3D full-vectorial finite-difference time domain (3D-FV-FDTD) for simulation verification. The simulated results show that the performance of the designed mode splitter meets the design targets, such as small size, low insertion loss and crosstalk, and large bandwidth. Thus the splitter can be applied to on-chip MDM systems, providing a viable device for high-capacity on-chip optical communications and optical interconnects.

Traditional design depends on the researchers' experience to achieve design goals by optimizing structure parameters. By contrast, the inverse design method is a goal-oriented approach that utilizes inverse algorithms to design various structures, which could reduce design complexity and improve design efficiency. We leverage an inverse design method to optimize the structure. The whole design process is divided into five steps as shown in Fig. 3, including initializing structure parameters, simulating and calculating gradient, binarization, designing for manufacturing, and exporting files. Step 1 is determining the design target and initializing structure parameters. The designed mode splitter is composed of three rectangular waveguides and a functional region (Fig. 1). Step 2 is simulating and calculating gradients. The adjoint algorithm can calculate the derivatives of all points in the space and requires only two simulation processes in each iteration. The derivatives of all points could fine-tune the structure. Step 3 is forcing the material index to values at the upper and lower bounds to create a structure that can be defined by etching. Step 4 is designing for manufacturing. The minimum feature size in the design is constrained based on the target photolithography process. The final step is exporting the files, where the mode splitter based on inverse design can separate the TE₀ mode and TE₁ mode, and the characteristics such as crosstalk, insertion loss, and fabrication tolerance are analyzed by the 3D-FV-FDTD method.

Simulation results show that the optimized mode splitter can efficiently separate the TE₀ mode and TE₁ mode. When the TE₀ mode is input, the insertion loss and crosstalk at the center wavelength are calculated to be 0.14 dB and -23.8 dB respectively, and when the TE₁ mode is input, the insertion loss and crosstalk are 0.48 dB and -22.45 dB respectively (Fig. 6). The operating bandwidth covers 150 nm, and the insertion losses of TE₀ and TE₁ modes are lower than 0.44 dB and 1.16 dB, respectively. Additionally, we analyze 13 mode splitters with fabrication errors from -30 nm to 30 nm. At the center wavelength, when the TE₀ mode is input, the insertion loss and crosstalk at the center wavelength are lower than 0.87 dB and -14.29 dB respectively, and when the TE₁ mode is input, the insertion loss and crosstalk are lower than 1.59 dB and -10.45 dB respectively (Fig. 6). The ±15 nm fabrication tolerance is analyzed based on the 3D-FV-FDTD method. The insertion losses of the two modes are lower than 0.79 dB, with the crosstalk lower than -18.37 dB (Fig. 7).

We propose and optimally design an on-chip silicon mode splitter based on the inverse algorithm incorporating an adjoint algorithm. The high performances of insertion loss and mode crosstalk are achieved within the operating wavelength from 1500 nm to 1650 nm. The optimized mode splitter can be obtained within 148 iterations, in which each iteration only requires two FDTD simulation steps. The simulation results show that at the center wavelength, the insertion loss and mode crosstalk of the TE₀ mode are less than 0.14 dB and -23.8 dB respectively, and those of the TE₁ mode are less than 0.48 dB and -22.45 dB respectively. The fabrication tolerances of the optimized mode splitter are also investigated with the fabrication errors of ±30 nm. A competitive performance can also be kept with an overall error of ±15 nm. A compact footprint of only 5.5 μm×4 μm and a wide operating bandwidth are realized. Our mode splitter could be applied to on-chip MDM systems, providing a viable device for high-capacity on-chip optical communications and optical interconnects.